Patent number 8610514 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "In recent years, the number of quadrature amplitude modulation (QAM) channels used for narrowcast digital television services has increased substantially. Most multiple system operators (MSOs) are providing more and more unicast QAM channels to support growth brought on by the success of video on demand (VOD) services. This has been driven, in large part, by an increase in offerings of high definition television services and content. Deployment of switched digital video (SDV) in order to provide an increased number of multicast content offerings is driving QAM channels even further. Additional QAM channels are also being deployed for MSOs cable modem termination system (CMTS) equipment.
"While the number of QAM channels is growing, MSOs are reducing the size of the service groups they offer to make more efficient use of their cable television networks. Smaller service groups result in improved service quality. Moreover, reusing spectrum available in a network is advantageous in that it supports narrowcast service growth.
"As a result of the above evolution in the CATV marketplace, more dense edge QAMs are required to reduce the cost of the equipment and the resulting environmental requirements in headends and distribution hubs. In order to help meet this need, a new equipment architecture option has been developed that enables the implementation of denser network architectures in a modular headend structure. Together with this, a new class of equipment is under development which is known as Converged Multiservice Access Platform (CMAP). CMAP implements the functions of the CMTS and edge QAM for all narrowcast and broadcast digital services. An introduction to CMAP can be found in the article Comcast Update: What is a CMAP,
"In order to implement a CMAP system, it is necessary to provide a suitable modulator to add digital television data to a carrier waveform using QAM. The prior art contains various different architectures for accomplishing this, but they all have drawbacks. Some known solutions utilize an older, less efficient method in terms of multiply operations per channel or operations per sample. Such methods are best described by FIGS. 1 and 2. FIG. 1 is a sub-block diagram of the signal processing chain for a single channel in a first prior art modulator architecture. FIG. 2 illustrates how this single channel architecture is replicated in parallel and summed in order to implement an entire downstream spectrum.
"As illustrated in FIG. 1, the modulator includes a symbol mapper 10, the output of which is provided to a first Square Root Raised Cosine Filter (SRRC) and interpolator 12 and a second SRRC and interpolator 14. The outputs of SRRC and interpolators 12 and 14 are provided to additional respective interpolators 16 and 20 which raise the output frequency of the signals to a range that is compatible with the sample rate of the downstream digital to analog converter (DAC) 28. The output of interpolator 16 is modulated with the sine function output from a digital quadrature oscillator 18 using mixer 22. The output of interpolator 20 is modulated with the cosine function output from the oscillator 18 using mixer 24. The outputs from the mixers 22, 24 are summed in adder 26, and the result is provided to a digital to analog converter (DAC) 28 in a conventional manner.
"FIG. 2 is a prior art example of the parallelization of single channel sub-blocks. This apparatus, generally designated 30, replicates the single channel architecture of FIG. 1 in parallel and sums the results. The output from the DAC represents the entire downstream spectrum.
"It is known (see, e.g., Harris, et al 'Digital Receivers and Transmitters Using Polyphase Filter Banks for
"As shown in FIG. 3, a plurality of channel streams 32a . . . 32n are input to a 720 point Inverse Discrete Fourier Transform (IDFT) processor 34. The output of processor 34 is resampled by a polyphase resampling filter 36 and then processed by a commutator 38 to produce output to be converted to analog by a digital-to-analog converter (DAC). The functions of the polyphase resampling filter 36 are to resample the channels to 6 MHz centers, provide matched filtering, and to provide channelization filtering. Such an implementation has several limitations for a modular CMAP (M-CMAP) system, which include: 1. For the number of filter taps per phase specified in FIG. 3, it can not meet the specifications for Adjacent Channel, Wideband Noise, and Carrier Suppression. To meet these specifications would require more than doubling the number of filter taps per phase and prohibit an efficient, cost effective solution. 2. It can not meet the 5 ppm frequency accuracy specifications. 3. It can only modulate a single mode (256 or 64 QAM) across all channels, whereas the CMAP specification requires mixed mode (simultaneous 64 and 256 QAM) operation across all channels. Specifically, if there are N total channels, the specification requires M channels of 64 QAM and K channels of 256 QAM, where K+M=N. 4. The Polyphase Resampler requires 720.times.47 REAL multipliers, which overly constrains the resources and layout for any potential FPGA implementation. 5. Only the STD frequency plan is provided using this design, whereas the HRC frequency plan is also required for M-CMAP
"It would be advantageous to provide an M-CMAP implementation in which these limitations are overcome. More particularly, it would be advantageous to provide a DSP implementation of a full spectrum DOCSIS/CATV downstream modulator that uses a single FPGA or ASIC and a single D/A converter. Still further, it would be advantageous for such an implementation to make use of the FFT based polyphase channelizer approach and which implements an IDFT by utilizing a DCT (Direct Cosine Transform) and DST (Direct Sine Transform) computation that is highly efficient and is computed based on an N/4 sized FFT kernel, wherein after the DCT/DST, the signal is converted from complex to real in order to both utilize a single DAC and exploit the corresponding reduction in complexity.
"The present invention provides methods and apparatus having the aforementioned and other advantages. Moreover, the unique combination of components/techniques disclosed herein provides various improvements over previously known structures and techniques."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventor's summary information for this patent: "A full spectrum modulator is provided which processes cable television signals or the like from a plurality of parallel channel processing paths. Each path has (i) a first filter for pulse shaping an input channel signal and upsampling a channel frequency thereof, (ii) an interpolator for interpolating the output of the first filter to a common sample rate, and (iii) a decimator for centering the output of the interpolator on a predetermined channel bandwidth that is related to the common sample rate. An Inverse Discrete Fourier Transform (IDFT) processor is coupled to receive channel signal outputs from the decimators of the plurality of parallel channel processing paths. A polyphase filter bank is coupled to receive IDFT processed parallel channel signals from the IDFT processor. A commutator converts the processed parallel channel signals from the polyphase filter bank to a single stream of data. A second filter upsamples the single stream of data to a fixed output sampling rate and low pass filters alias signals therefrom.
"The modulator can be implemented for use with a standard cable television channel frequency plan. In such an implementation, the parallel channel processing paths can comprise a direct digital synthesizer (DDS) coupled between the interpolator and the decimator to add a carrier offset to signals input to the decimator from the interpolator. Such an implementation further includes a complex to real signal processor between the IDFT processor and the polyphase filter bank.
"The IDFT processor can be, for example, a 360 point IDFT processor. The first filter is preferably a square root raised cosine (SRRC) filter with 1:2 upsampling. The interpolator can comprise a Farrow six tap cubic interpolator. The decimator can be a 2:1 decimator. The second filter can comprise an upsampling half band filter (HBF) with 1:2 upsampling.
"A modulator can also be provided in accordance with the invention for use with a harmonically related carrier (HRC) cable television channel frequency plan. In this case, the IDFT processor is preceded by a cross bar switch adapted to flip the channel signal outputs from the decimators prior to input to the IDFT processor. In such an implementation, the second filter can consist of a high pass filter, a down converter following the high pass filter, and a low pass filter following the down converter. More specifically, the second filter can comprise a high pass half band filter (HBF), a direct digital synthesizer (DDS) down converter following the high pass filter, and a low pass half band filter following the down converter.
"Like the standard cable television channel frequency plan implementation, in the HRC implementation the IDFT processor can be a 360 point IDFT processor and the first filter can be a square root raised cosine (SRRC) filter with 1:2 upsampling. The interpolator can comprise, e.g., a Farrow six tap cubic interpolator, and the decimator can be a 2:1 decimator. The second filter can comprise a high pass filter, a down converter following the high pass filter, and a low pass filter following the down converter. It should be appreciated that other types of interpolators, decimators and filter arrangements can alternatively be used. Choices of other implementations will depend, for example, upon the allocation of performance margins across all of the blocks in the modulator.
"A method is provided for modulating a plurality of cable television channel signals each having a channel frequency. In accordance with the method, each of the channel signals is pulse shaped and then the channel frequency of each pulse shaped signal is upsampled. The pulse shaped, upsampled signals are interpolated to a common sample rate. The interpolated signals are then centered to a predetermined channel bandwidth that is related to the common sample rate. An Inverse Discrete Fourier Transform (IDFT) is performed on each of the channel signals. The channel signals are polyphase filtered after the IDFT. The filtered channel signals from the polyphase filter bank are then converted into a single stream of data, which is upsampled to a fixed output sampling rate. The upsampled single stream of data is low pass filtered to remove alias signals therefrom.
"In a first implementation for use with a standard cable television channel frequency plan, the method of the invention adds a carrier offset to the interpolated signals provided by the interpolating step. The signals are converted from complex to real between the IDFT and polyphase filtering steps.
"A method is also provided for use with a harmonically related carrier cable television channel frequency plan. In such an implementation, the frequency spectrums of the channel signals are flipped between the centering and IDFT steps. The single stream of data is high pass filtered during the second upsampling step, and then the high pass filtered single stream of data is down converted prior to the low pass filtering step."
URL and more information on this patent, see: Laudel, Kennan. Full Spectrum Modulator for Digital Television Signals. U.S. Patent Number 8610514, filed
Keywords for this news article include: Electronics,
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