Patent number 8610613 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "The present invention relates to semiconductor integrated circuit devices, and in particular relates to the technique effectively applied to a semiconductor integrated circuit device with an analog/digital conversion circuit block having a disconnection detection function.
"Japanese Patent Laid-Open No. 1987-86724 (Patent Document 1) describes a configuration, in which in a signal combining circuit for combining an actual line and an auxiliary line at one terminal, a T-type switch is arranged in each of the actual line and the auxiliary line. This T-type switch includes a first switch and a second switch connected in series over the line, a third switch connected between the common connection node of the first and second switches and a ground power supply voltage, and additionally a resistor connected in parallel to the first switch. In switching the actual line and the auxiliary line, each switch is appropriately controlled."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "An analog/digital conversion circuit block mounted on a semiconductor integrated circuit device (LSI), such as a microcontroller (MCU), usually includes a plurality of switches for coupling either of channels to a common analog/digital conversion circuit (ADC). FIGS. 29A to 29C are circuit diagrams each of which shows a different switch configuration in a semiconductor integrated circuit device which has been examined as a prerequisite of the present invention. FIG. 29A shows a CMOS switch circuit CS. In this circuit, the source/drain paths of a PMOS transistor MP1 and an NMOS transistor MN1 are connected in parallel between an input node IN and an output node OUT. A clock signal CLK and an inverted clock signal (/CLK) controls MN1 and MP1.
"FIG. 29B shows a T-type switch circuit TS' including three PMOS transistors MP1, MP2, and MPc and three NMOS transistors MN1 and MN2, and MNc. The source/drain paths of MN1 and MN2 are connected in series between the input node IN and the output node OUT. The source/drain paths of MP1 and MP2 are connected in series between IN and OUT. MPc pulls up the voltage VN of a common connection node of MN1 and MN2 to an analog power supply voltage VCCA. MNc pulls down the voltage VP of a common connection node of MP and MP2 to an analog ground potential VSSA. The clock signal CLK controls MN1, MN2, and MPc. The inverted clock signal (/CLK) controls MP1, MP2, and MNc.
"When TS' is in an on state, MN1, MN2, MP1, and MP2 are turned on and MPc and MNc are turned off. When TS' is in an off state, MN1, MN2, MP1, and MP2 are turned off and MPc and MNc are turned on. Then, VN is pulled up to VCCA and VP is pulled down to VSSA. This configuration can achieve a high isolation between IN and OUT when TS' is in an off state. If a high current flows from the IN side, most of the current flows via MPc or MNc, and MN2 and MP2 remain to be in an off state. Also, a leak to the OUT side (serving as an input terminal of ADC) is unlikely to occur.
"FIG. 29C shows a T-type switch circuit ETS' with an equalizer. In this circuit, an equalizing switch is added to the configuration in FIG. 29B. The equalizing switch includes an NMOS transistor MN3 and a PMOS transistor MP3 whose source/drain paths are connected in parallel between the common connection node of MN1 and MN2 and the common connection node of MP1 and MP2. CLK drives MN3. (/CLK) drives MP3. In TS' in FIG. 29B, when TS' transitions from an off state to an on state along with the sampling by ADC, VN and VP differ in electric potential in the initial transition stage and moreover a current for setting VN and VP to the same electric potential may flow even just before the sampling ends. This current causes a voltage drop via a signal source resistance connected to the input section of a channel, causing a conversion error of ADC. The configuration in FIG. 29C can set VN and VP to the same electric potential when ETS' is on. Also, the conversion error of ADC is unlikely to occur.
"Recently, such an analog/digital conversion circuit block is requested to have a disconnection detection function for detecting the presence or absence of a disconnection in an external wiring of each channel. FIG. 30 is a circuit diagram showing a configuration of the major portion around an analog/digital conversion circuit block in a semiconductor integrated circuit device, which has been examined as a prerequisite of the present invention. In FIG. 30, A and A are input ports for connecting the semiconductor integrated circuit device (LSI), such as a MCU, to an external circuit. This circuit has two channels of input ports.
"As shown in the LSI in FIG. 29B, A is connected to an input terminal
"When an analog signal (Vint) of the channel is converted into a digital signal, TS' is turned on and TS' is turned off. When an analog signal (Vint) of the channel is converted into a digital signal, TS' is turned on and TS' is turned off. It is preferable to use a T-type switch circuit with high isolation characteristics (or a T-type switch circuit with an equalizer) so that no sampling by ADC for a first channel (channel) affect the analog signal of a second channel (channel).
"The above-mentioned disconnection detection function is a function to detect the presence or absence of a disconnection between A and Vint or between A and Vint. FIG. 30 shows that a disconnection is between A and Vint and no disconnection is between A and Vint. First, before the disconnection detection, the voltage Vb of
"Next, Vb is assumed to be pre-charged to VCCA and subsequently only TS' is assumed to be turned on. Because the external wiring is connected, the impedance (the resistance of Ra) between A and Vint  is about 0 to 1 K.OMEGA. and the impedance (the resistance of Rb) between A and Rb is about 1 M.OMEGA.. Because Rb is higher than Ra, the electrical potential of Vb becomes about Vint. Accordingly, the presence or absence of a disconnection can be determined by analog/digital conversion (A/D conversion) of the resulting Vb by ADC. If VCCA is output in a digital code, a disconnection is determined. If a digital code of Vint or Vint is output, the absence of a disconnection is determined.
"However, the present inventors have found that a reliable disconnection detection may not be performed if the disconnection detection is performed by using the configuration and operation as described in FIG. 30. FIG. 31 is a waveform chart showing an operation during the disconnection detection by using the configuration in FIG. 30. As shown in FIG. 31, before the disconnection detection for the channel, the electric potential of Vb is pre-charged to VCCA by MPu. At this time, due to an off state of TS', VN is set to VCCA, VP is set to be VSSA, and VP and Vb differ in the electric potential. When TS' transitions to an on state along with the start of disconnection detection, a current IT flows to charge VP. The current IT causes a voltage drop in the resistor Rb, causing an A/D conversion error in VCCA by (ITxRb). As a result, an error may in the disconnection detection result.
"If the sampling period by ADC can be lengthened, Vb converges on VCCA at a predetermined time constant and thus the disconnection detection can be performed without any problem. However, to speedup the analog/digital conversion circuit block, the sampling period should not be preferably lengthened. The sampling period by ADC can be lengthened only during disconnection detection. However, in this case, the time required for disconnection detection significantly increases as the multichannel progresses. Additionally, a dedicated control sequence using a dedicated timing clock needs to be provided separately, which may increase the circuit or complexes the control. Moreover, in the automobile application or the like, MPc and MNc may need to extract a large current which is generated by a battery and then unintentionally injected into an input port. In this case, the transistors MPc and MNc become large. Then, a time constant until Vb converges on VCCA becomes very large, and the time required for disconnection detection significantly increases.
"Furthermore, such a problem becomes more prominent as accuracy is high in addition to that the multichannel progresses and the analog/digital conversion circuit block speeds up. In the configuration in FIG. 30, an error corresponding to a ratio of the resistor Ra (Ra and Ra) and the resistor Rb (Rb and Rb) occurs during the normal A/D conversion. To increase accuracy, the resistance of Rb is preferably larger than that of Ra. Then, the voltage drop due to the current IT and Rb increases and moreover a time constant for Vb to return to VCCA also increases. Reliable disconnection detection may become more difficult.
"The present invention has been made in view of the above circumstances. One of the purposes is to achieve reliable disconnection detection in a semiconductor integrated circuit device with an analog/digital conversion circuit block. The other purposes and the new feature of the present invention will become clear from the description of the present specification and the accompanying drawings.
"The following explains briefly the outline of an embodiment of a typical invention among the inventions disclosed in the present application.
"A semiconductor integrated circuit device in accordance with an embodiment includes an input port; a first MIS transistor and a second MIS transistor in which one end of a source/drain is connected to the input port; a first wiring path for connecting a second end of the source/drain of each of the first and second MIS transistors to a first node; and an analog digital conversion circuit, and performs a first cycle and a second cycle. The input port is connected to a first power supply voltage via a first external resistor, and is also connected to an analog signal input terminal to be measured via a second external resistor whose resistance is lower than that of the first external resistor. The first MIS transistor and the second MIS transistor differ in conductivity. The analog/digital conversion circuit converts the voltage of the first node into a digital signal. The first and second cycles are executed in this order to detect the presence or absence of a disconnection in a path from the analog signal input terminal to the input port. In the first cycle, the first and second MIS transistors are turned off and the first wiring path is pre-charged to the first power supply voltage. In the second cycle, the first and second MIS transistors are turned on and the analog/digital conversion circuit operates.
"when a disconnection is in this semiconductor circuit, almost no current flows through the first external resistor. It is because no electric potential difference occurs at the both ends of the first and second MIS transistors when the cycle transitions from the first cycle to the second cycle. This can reduce a conversion error of the analog/digital conversion circuit caused by the voltage drop of the first external resistor, so a reliable disconnection detection can be performed.
"The following explains briefly the effect acquired by the typical invention among the inventions disclosed in the present application. In a semiconductor integrated circuit device with an analog/digital conversion circuit block, a reliable disconnection detection can be performed."
URL and more information on this patent, see: Ebata, Tomohiko; Aso, Takuji. Semiconductor Integrated Circuit Device. U.S. Patent Number 8610613, filed
Keywords for this news article include: Semiconductor,
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