Patent number 8610248 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "The presented application relates to a capacitor structure and a method for manufacturing the same, in particular, to an integrated capacitor structure using in an embedded memory device and a method of manufacture.
"There is a great demand for an integrated capacitor formed on a substrate in the field such as cellular phones. The integrated capacitor can be used in an analogous circuit and an RF circuit where a capacitance value of above pF is typically required. However, the maximum value of planar capacitance density, which can be achieved in the current integrated circuit process, is about tens of fF/.mu.m.sup.2. In order to achieve the capacitance value of above pF, the resultant capacitor must have a relatively large footprint on the chip. This decreases an integration level, and causes an undesired parasitic effect due to those wirings having an increased length. Moreover, when used in an embedded memory (such as eDRAM) in a digital circuit, the capacitance value of a memory cell is of critical importance to a retention time of the device. In order to achieve a retention time as long as possible for each memory cell, an integrated capacitor should have a capacitance density as large as possible.
"However, the eDRAM cell comprising a deep trench capacitor still has many difficulties in manufacturing process. For example, since a deep trench has a high aspect ratio, a reactive ion etching (RIE) process will take a long time for forming the deep trench, and voids possibly exist in the following metal filling process.
"Consequently, the deep trench capacitor has a high manufacturing cost and a poor reliability.
"On the other hand, the above difficulties in the manufacturing processes limit the depth of the trench to be formed. The resultant capacitance value is too small to provide a desired retention time of the eDRAM cell.
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "An object of the present invention is to provide an integrated capacitor structure having a small footprint on a chip and to be manufactured easily.
"According to one aspect of the invention, there provides a capacitor structure, comprising, a plurality of sub-capacitors stacked on a substrate, each of which comprises a top capacitor plate, a bottom capacitor plate and a dielectric layer sandwiched therebetween; and a first capacitor electrode and a second capacitor electrode connecting the plurality of sub-capacitors in parallel, wherein the plurality of sub-capacitors include a plurality of first sub-capacitors and a plurality of second sub-capacitors stacked in an alternate manner, each of the first sub-capacitors has a bottom capacitor plate overlapping with a top capacitor plate of an underlying second sub-capacitor, with the overlapping plate being a first electrode layer; and each of the second sub-capacitors has a bottom capacitor plate overlapping with a top capacitor plate of an underlying first sub-capacitors, with the overlapping plate being a second electrode layer, the capacitor structure is characterized in that the first electrode layer and the second electrode layer are made of different conductive materials.
"According to another aspect of the invention, there provides a method for manufacturing a capacitor structure, comprising the steps of:
"a) forming an insulating layer on a semiconductor substrate;
"b) forming repeated stacks of a first electrode layer, a first dielectric layer, a second electrode layer, and a second dielectric layer in an alternate manner on the insulating layer so as to form a multi-layer structure;
"c) etching a first side of the multi-layer structure, in which the exposed portion of the second electrode layer at the first side is selectively removed with respect to the first electrode layer, the first dielectric layer, and the second dielectric layer, so that recesses remain at the first side; d) etching a second side of the multi-layer structure, in which the exposed portion of the first electrode layer at the second side is selectively removed with respect to the first dielectric layer, the second electrode layer, and the second dielectric layer, so that recesses remain at the second side; e) forming a capping layer of insulating material on the multi-layer structure; f) forming capacitor openings in the capping layer, which expose the first side and the second side of the multi-layer structure, and in which the insulating material remains in the recesses at the first side and the second side; and g) filling the capacitor openings with a conductive material.
"The inventive capacitor structure has a small footprint on the chip and a large capacitance value because a plurality of sub-capacitors are stacked and connected in parallel with each other. Moreover, the capacitor structure may have a desired capacitance value by changing the number of the stacked sub-capacitors. This provides an additional degree of freedom in the design of the capacitor structure.
"Preferably, the capacitor structure is provided in shallow trench isolation (STI) so that it does not adversely affect the degree of freedom in the design of active devices.
"Moreover, since the first electrode layer and the second electrode layer are made of different materials, the capacitor structure can be formed in etching steps by using masks, which is compatible with the conventional integrated circuit process.
"Preferably, the multi-layer structure is mainly formed in Front-End-Of-Line (FEOL), including the steps of depositing dielectric layer and conductive layers, which is compatible with the conventional process, with only some additional masking steps and depositing steps incorporated. More preferably, capacitor openings are formed in Middle-Of-Line (MOL), simultaneously with the formation of contact holes. No additional masking and depositing steps are needed."
URL and more information on this patent, see: Liang, Qingqing; Zhong, Huicai. Capacitor Structure and Method of Manufacture. U.S. Patent Number 8610248, filed
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