"DRC enables a designer to verify the correctness of his or her design and to achieve a high overall yield and reliability for the design. In other words, a routing solution, for example, is usually driven by various design rules against which the electronic design may be checked and a set of requirements such as spacing requirements between two or more objects and routing object size requirements. The routing applications such as a router then ensure that these design rules and various sets of requirements are met in order to have a working electronic circuit. For example, DRC governs how an object has to be spaced relative to another object and to meet the width requirement. That is, after the physical mask layout is generated for an electronic circuit, the layout is measured by a set of constraints, rules, or requirements, such as geometric constraints or rules for the particular processes the electronic circuit is designed to perform, to ensure high yield and reliability by verifying that the electronic design meets the process constraints.
"An electronic circuit often comprises a plurality of blocks or modules which are highly state-dependent because the actions of the plurality of blocks or modules depend not only on their inputs but also on what events have previously happened. The electronic circuit components, or, more precisely, the geometries in the electronic circuit design in a verification flow, such as a design rule checking process, are usually grouped into layers. Depending upon the type of verification operations, typical examples of such layers comprise drawn layers which represent the original layout data, polygon layers each of which constitutes the output of a layer creation operation such as a Boolean operation, an area function, or a polygon operation. Typical examples of such layers may also comprise edge layers, each of which represents one or more edges of merged polygons as outputted by operations such as some measurement operations. Another exemplary layer is an error layer which comprises a set of one or more edges from a measurement operation.
"Such a hierarchical design for an electronic circuit defines the underlying circuit as a plurality of smaller modules, blocks, cells, or cellviews, each of which may be further broken down to comprise another set of even smaller sub-modules or sub-blocks and eventually down to individual circuit elements or components such as individual pieces of interconnects. This hierarchical nature of the electronic design allows the circuit designers not only to consider the entire electronic circuit in a modular way but also to consider each of the modules, blocks, sub-modules, sub-blocks, or the individual circuit elements individually, if desired. In addition, this hierarchical design allows for scoping for variable declaration, procedure calls, and/or policy determination for each of the various levels in the hierarchy.
"Conventional approaches for verification of electronic circuits such as language-based DRC or image-based DRC operate upon a flat design. It is noted that a flat design may be considered as an electronic design with one cell in the sense that every circuit element in the electronic design belongs to the single cell. With these conventional approaches, a cell-based hierarchical input for an electronic design is flattened, and the entire design is internally represented as one large cell. The language-based DRC (such as a rule-based DRC or a model-based DRC) or an image-based DRC is then performed against this flattened design.
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