"The time needed to finish processing every row of data defines the upper limit of the frame rate of dynamic images.
"JP-A-2002-44527 (Patent Document 1) and JP-A--2006-49361 (Patent Document 2) have proposed an image sensor which has a laminate of pixels and AD converters.
"FIG. 2 is a conceptual diagram of a CMOS image sensor 10A which has a laminate of pixels and AD converters.
"To help understand the concept, same reference numerals are given to the same components as shown in FIG. 1.
"The CMOS image sensor 10A in FIG. 2 has pixels PX and AD converters 13 respectively arranged on different semiconductor substrates in an array. The two semiconductor substrates are laminated one on the other, with each pixel connected to the respective AD converter by an analog signal line 17.
"The use of such an architecture can ensure reading charges from multiple rows of pixels at a time, and parallel execution of AD conversion row by row.
"The data after conversion is temporarily transferred to a memory 19 to be transferred to an image processing apparatus (not shown) located inside or outside the chip.
"The adoption of such a laminate structure can dramatically improve the imaging speed at least in the imaging chip, thereby ensuring ultrafast frame imaging.
"Further, development of a high-precision wafer adhering technique has lately attracted considerable attention. For example, JP-A-2007-234725 (Patent Document 3) and JP-A-2006-191081 (Patent Document 4) describe a technique of adhering a back-irradiation type image sensor and a circuit-mounted substrate opposite to each other, and transfer signals therebetween via a metal pad.
"This technique makes it possible to prepare a laminate structure as shown in FIG. 2 in the wafer-level fabrication, and connect pixels to AD converters without implementing bump connection for each chip.
"Since this technique allows individual chips to be cut out after the wafer-level fabrication, it is suitable for microprocessing and is considerably inexpensive.
"JP-A-7-67043 (Patent Document 5) has proposed a new scheme of counting photons in a time-divisional manner.
"According to the counting scheme, binary decision on the presence/absence of a photon input to a photodiode in a given period is repeatedly performed multiple times, and the decision results are integrated to acquire two-dimensional imaged data.
"That is, signals from the photodiode in the given period are sensed, and a counter connected to each pixel is counted up by 1, regardless of the number of input photons when the number of photons input in that period is equal to or greater than 1.
"If the frequency of photon inputs is random along the time axis, the actual number of photons input and the count number are conform to the Poisson distribution, so that the numbers have a substantially linear relation when the incident frequency is low, and can be corrected in any case when the incident frequency is high.
"Since the image sensor using such time-divisional photon counting treats data output from the pixels always as digital data, random noise or fixed nose originated from transmission and amplification of analog signals do not occur.
"At this time, it is only the photo shot noise and dark current generated in the pixels that remain, and a very high S/N ratio can be acquired particularly in imaging with low illuminance."
Supplementing the background information on this patent, VerticalNews reporters also obtained the inventor's summary information for this patent: "The use of the structure in FIG. 2 can allow signals to be read out from the pixel array section fast in parallel and be subjected to AD conversion before being stored as data in the memory.
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