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Patent Issued for Semiconducting Multi-Layer Structure and Method for Manufacturing the Same

September 10, 2014



By a News Reporter-Staff News Editor at Journal of Engineering -- Macronix International Co., Ltd. (Hsinchu, TW) has been issued patent number 8816423, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventors are Lai, Erh-Kun (Taichung, TW); Shih, Yen-Hao (New Taipei, TW).

This patent was filed on August 13, 2012 and was published online on August 26, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "The invention is related to a semiconducting multi-layer structure and method for manufacturing the same, and more particularly to a semiconducting multi-layer structure of a memory device.

"The demand of memory devices increases complying with a growth in market of the electronic products. There are several types of memory devices, such as volatile and non-volatile memory (NVM) devices.

"The dynamic random access memory (DRAM) and the cache memory are volatile memories. Although a read access velocity of a volatile memory is fast, a non-volatile memory can be used as a hard disk since data stored in non-volatile memories will exist even when the current pinch off. According to read/write characteristic differences of memory devices, the non-volatile memory can be separated into read only memory (ROM) and flash memory. Recently, flash memory has been widely used in a variety of filed, such as cell phone, digital camera and MP3.

"In order to increase a storage capacity of the memory in a limited memory volume, a three dimensional (3D) memory is developed. In a 3D memory, pitches between each elements are smaller and an element density in an unit area of the 3D memory is larger."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "The invention is related to a semiconducting multi-layer structure and method for manufacturing the same. A current channel can be formed in the semiconducting multi-layer structure, without operating an ion implantation process to the semiconducting multi-layer structure.

"According to a first aspect of the present invention, a semiconducting multi-layer structure comprising a plurality of first conductive layers, a plurality of first insulating layers and a second conductive layer is disclosed. The first conductive layers are separately disposed. Each of the first conductive layers has an upper surface, a bottom surface opposite to the upper surface and a lateral surface. The first insulating layers surround the peripherals of the first conductive layers. Each first insulating layer covers at least a part of the upper surface of each of the first conductive layers, at least a part of the bottom surface of each of the first conductive layers and the lateral surface of each of the first conductive layers. The second conductive layer covers the first conductive layers and the first insulating layers.

"According to a second aspect of the present invention, a method for manufacturing a semiconducting multi-layer structure, comprising following steps is disclosed. A plurality of first conductive layer spaced apart from each other are forming. Each of the first conductive layers has an upper surface, a lower surface opposite to the upper surface and a lateral surface. A plurality of first insulating layers surrounding peripherals of the first conductive layers are formed. Each of the first insulating layers covers at least a part of the upper surface, a part of the lower surface and the lateral surface of the first conductive layer. A second conductive layer covering the first conductive layers and the first insulating layers is formed.

"According to a third aspect of the present invention, a semiconducting multi-layer structure used in a memory device is disclosed. The semiconducting multi-layer structure comprises a plurality of conductive layers, a plurality of gate oxide layers and a gate layer. The conductive layers are spaced apart from each other. Each of the conductive layers has an upper surface, a lower surface opposite to the upper surface and a lateral surface. The gate oxide layers surround peripherals of the conductive layers. Each of the gate oxide layers covers at least a part of the upper surface, a part of the lower surface and the lateral surface of the conductive layers. The gate layer covers the conductive layers and the gate oxide layers.

"The above and other aspects of the invention will become better understood with regard to the following detailed description of the preferred but non-limiting embodiment(s). The following description is made with reference to the accompanying drawings."

For the URL and additional information on this patent, see: Lai, Erh-Kun; Shih, Yen-Hao. Semiconducting Multi-Layer Structure and Method for Manufacturing the Same. U.S. Patent Number 8816423, filed August 13, 2012, and published online on August 26, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8816423.PN.&OS=PN/8816423RS=PN/8816423

Keywords for this news article include: Macronix International Co., Macronix International Co. Ltd.

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Source: Journal of Engineering


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