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Patent Issued for Sampling Circuit, a Method of Reducing Distortion in a Sampling Circuit, and an Analog to Digital Converter Including Such a...

September 10, 2014



Patent Issued for Sampling Circuit, a Method of Reducing Distortion in a Sampling Circuit, and an Analog to Digital Converter Including Such a Sampling Circuit

By a News Reporter-Staff News Editor at Journal of Engineering -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventors Hurrell, Christopher Peter (Berkshire, GB); Maurino, Roberto (Turin, IT), filed on September 21, 2012, was published online on August 26, 2014.

The patent's assignee for patent number 8816887 is Analog Devices, Inc. (Norwood, MA).

News editors obtained the following quote from the background information supplied by the inventors: "In sample and hold circuits, it is generally desirable to provide an electrically operated switch that notionally switches between high impedance (off) and low impedance (on) states.

"One switch technology that is suited for use in precision converters is a 'transmission gate' arrangement. However, such a configuration is made with real field effect transistors whose drain-source resistance R.sub.DSon varies with the input voltage at an input terminal of the transmission gate. Therefore in the context of a sampling circuit comprising a transmission gate in series with a sampling capacitor, the series resistance of the transmission gate varies with input voltage, and this is a source of distortion, degrading the total harmonic distortion performance of the sampling circuit, and of subsequent or associated devices such as analog to digital converters.

"The 'on' resistance of the FETs making up the transmission gate can be reduced by making the transistors wider. However this increases the values of parasitic capacitances associated with the transistor switches, which themselves are non-linear, resulting in an increase in distortion from a secondary distortion mechanism resulting from an interaction between the non-zero impedance of a signal source driving the sampling circuit (whether the operation of the sampling circuit is a 'sample and hold' or 'track and hold' style of operation) and this increased non-linear capacitance."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "According to a first aspect of the present invention there is provided a sampling circuit comprising: an input node; a first signal path comprising a first sampling capacitor and a first signal path switch in a signal path between the input node and a first plate of the first sampling capacitor; a second signal path comprising a second sampling capacitor and a second signal path switch in a signal path between the input node and a first plate of the second sampling capacitor, and a signal processing circuit for forming a difference between a signal sampled onto the first sampling capacitor and a signal sampled onto the second sampling capacitor.

"In an embodiment of the invention, the first and second capacitors have dissimilar capacitances and/or the switches are fabricated to have dissimilar on resistances. This gives rise to dissimilar sized errors due to the on resistance of the switches. With appropriate selection of component values the error can be estimated or the errors in the first and second channels can be arranged to substantially cancel each other.

"A sampling capacitor may be formed as a sum of a plurality of capacitors. The plurality of capacitors may be associated with respective switches such that they can be switched into and out of various combinations with each other, for example, as part of a successive approximation conversion.

"Advantageously the switches are formed by field effect transistors. The first switch may be formed from at least one NMOS transistor forming an NMOS switch in parallel with at least one PMOS transistor forming a PMOS switch.

"Similarly the second switch may be formed from at least one NMOS transistor forming an NMOS switch in parallel with at least one PMOS transistor forming a PMOS switch.

"In an embodiment the NMOS switch in the first switch comprises parallel connected NMOS transistors, whereas the NMOS switch in the second switch comprises series connected NMOS transistors. The switches may also comprise parallel and series connected PMOS transistors respectively.

"According to a further aspect of the present invention there is provided a method of correcting for voltage errors in a sampling network, comprising forming two sampling networks where at least one of the capacitances and switch resistances vary between one network and the other such that dissimilar sampling errors occur, and processing the dissimilar errors so as to estimate or to remove the sampling error from a sample result."

For additional information on this patent, see: Hurrell, Christopher Peter; Maurino, Roberto. Sampling Circuit, a Method of Reducing Distortion in a Sampling Circuit, and an Analog to Digital Converter Including Such a Sampling Circuit. U.S. Patent Number 8816887, filed September 21, 2012, and published online on August 26, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8816887.PN.&OS=PN/8816887RS=PN/8816887

Keywords for this news article include: Analog Devices, Analog Devices Inc., Medical Device Companies, Medical Device Company.

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Source: Journal of Engineering


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