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Patent Issued for Data Processing Apparatus and Method for Performing Memory Transactions within Such a Data Processing Apparatus

September 9, 2014



By a News Reporter-Staff News Editor at Information Technology Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventor Craske, Simon John (Cambridge, GB), filed on November 14, 2011, was published online on August 26, 2014.

The assignee for this patent, patent number 8819378, is ARM Limited (Cambridge, GB).

Reporters obtained the following quote from the background information supplied by the inventors: "The present invention relates to a data processing apparatus, and to a method for performing memory transactions within such a data processing apparatus.

"Instruction sets provided for execution on the data processing apparatus, such as a processor core, will typically include a number of memory access instructions that, when executed, cause a memory transaction to be performed to move data between memory addresses in the memory address space and registers of a register file within the data processing apparatus. One type of memory access instruction is a store instruction used to store data from the register file to a specified memory address within the memory address space. Another example of a memory access instruction is a load instruction used to load data from a specified memory address in the memory address space into one or more registers of the register file.

"The memory address space can be partitioned in a variety of ways, and hence whilst one or more portions of the memory address space may be reserved for actual memory, other portions of the memory address space may be associated with storage provided within devices other than memory. For example, a portion of the memory address space may be associated with storage within a display controller, another portion of the memory address space may be associated with storage within a universal asynchronous receiver/transmitter (UART) device used to translate data between parallel and serial forms (for example to allow serial communications over a computer or peripheral device serial port), etc.

"Traditionally, a data processing apparatus such as a processor core would communicate with all of the devices associated with the memory address space via a single interface. Accordingly, within an integrated circuit containing the processor core, the processor core may have a single system interface for connecting the processor core to a system bus to which the various memory address space associated devices are also coupled.

"More recently, it is known to provide a processor core with more than one interface via which communications with memory address space associated devices can be achieved. This hence allows the processor core to be coupled to different buses, employing different bus protocols. Memory accesses can then be directed via the appropriate interface, dependent on which bus the device being accessed is connected to.

"Typically, different bus protocols have different characteristics, and hence by providing more than one bus, increased flexibility is provided with regard to how individual devices are coupled to the processor core, thereby for example allowing certain devices to be connected to a bus allowing higher throughput, whilst other devices are connected to a bus allowing higher latency, etc.

"In systems where the processor core has more than one interface via which memory accesses can be performed, there have typically been two approaches for handling such memory accesses. In accordance with the first approach, the memory access instructions within the instruction set do not distinguish between the different interfaces being used, and hence any particular memory access instruction is executed in the same way, irrespective of which interface is being used to handle the required memory transaction for that memory access instruction. The separate interfaces then include the required circuitry to control performance of the memory transaction having regard to the relevant bus protocol. Hence, in such embodiments, the internal signals passing between the processing circuitry executing the memory access instruction and the relevant interface circuitry are identical irrespective of which interface circuitry is being used. This simplifies the operation of the processor core, but does not allow the processor core to take advantage of any of the performance benefits that may be associated with one of the interfaces. For example, if one of the interfaces is connected to a bus which can process memory transactions more quickly than the bus to which the other interface is connected, this performance benefit cannot be used to realise any performance benefit within the processor core itself, since the internal handling of the memory access instruction within the processor core is the same, irrespective of which interface is used.

"An alternative approach which can be taken is to provide separate memory access instructions associated with the different interfaces. Hence, for a memory access to be performed via a first interface, a first type of memory access instruction may be used, whilst for an equivalent memory access to be performed via a second interface, a separate second type of memory access instruction may be used. Whilst this can allow the processor core to internally take advantage of any performance benefits that one interface may provide relative to the other interface, it significantly increases programming complexity, and hence is difficult to use in practice.

"Accordingly, it would be desirable to provide an improved mechanism for performing memory transactions within a data processing apparatus, which allows the data processing apparatus to take advantage of performance benefits that may be available when using one interface, but without the requirement for separate memory access instructions to be provided within the instruction set in association with each memory interface."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventor's summary information for this patent: "Viewed from a first aspect, the present invention provides a data processing apparatus comprising: processing circuitry configured to execute a sequence of instructions including a memory access instruction, the processing circuitry including memory control circuitry configured to execute said memory access instruction to generate a memory transaction comprising at least one address transfer specifying a memory address and at least one associated data transfer specifying data to be accessed at the specified memory address; a first interface and a second interface; the memory control circuitry being configured to route each address transfer and associated data transfer via the first interface when the specified memory address is within a first memory address range, and to route each address transfer and associated data transfer via the second interface when the specified memory address is within a second memory address range; the memory control circuitry further being configured, when using the first interface, to execute the memory access instruction so as to cause each address transfer and associated data transfer to be presented at the first interface with a first relative timing; and the memory control circuitry further being configured, when using the second interface, to modify execution of the memory access instruction so as to cause each address transfer and associated data transfer to be presented at the second interface with a second relative timing different to said first relative timing.

"In accordance with the present invention, the data processing apparatus has a first interface and a second interface, and the memory control circuitry used to execute the memory access instruction routes each address transfer and associated data transfer of the corresponding memory transaction via the first interface or via the second interface, dependent on the memory address specified for that memory access instruction. When the first interface is being used, the memory control circuitry executes the memory access instruction so as to cause each address transfer and associated data transfer to be presented at the first interface with a first relative timing. In contrast, when the second interface is being used, the memory control circuitry modifies execution of the memory access instruction so as to cause each address transfer and associated data transfer to be presented at the second interface with a second relative timing different to the first relative timing.

"Hence, in accordance with the present invention, by executing the same memory access instruction differently dependent on which interface is being used for handling the memory transaction, the data processing apparatus is able to take advantage of any performance benefit available when using one of the interfaces rather than the other, without interface-specific memory access instructions being provided within the instruction set.

"The memory address range associated with each interface does not need to specify a single continuous sequence of addresses, and instead multiple sub-ranges of addresses and/or individual addresses may collectively constitute the memory address range.

"The memory control circuitry can be arranged in a variety of ways. However, in one embodiment, the memory control circuitry comprises buffer circuitry selectively employed during modified execution of the memory access instruction to achieve the second relative timing of each address transfer and associated data transfer as presented at the second interface. Hence, by internally buffering certain signals within the data processing apparatus, this allows each address transfer and associated data transfer to be presented at the second interface with the second relative timing (in this example it being assumed that the second relative timing provides a performance improvement when compared with the first relative timing), whilst freeing up resources within the data processing apparatus to enable advantage to be taken of the performance improvement (for example by increasing instruction throughput).

"The first and second relative timings can take a variety of forms. However, in one embodiment, in accordance with the first relative timing, the memory control circuitry is configured to cause each address transfer and associated data transfer to be presented at the first interface during different clock cycles, whilst in accordance with the second relative timing, the memory control circuitry is configured to use the buffer circuitry in order to cause each address transfer and associated data transfer to be presented at the second interface during the same clock cycle.

"In one embodiment, the memory control circuitry includes an address generator configured to generate the memory address for each address transfer, and the memory control circuitry is configured for at least one type of memory transaction, when using the second interface, to buffer each memory address generated by the address generator within the buffer circuitry for at least one clock cycle, such that each address transfer and associated data transfer is presented at the second interface during the same clock cycle.

"Such an approach is beneficial if the computation required to create the relevant data transfer cannot be completed within the same cycle as the address transfer, for example because it takes more than one clock cycle to generate the required data transfer. In one embodiment, such a scenario arises when the memory transaction is a multi-beat memory transaction comprising multiple address transfers and associated data transfers, and hence for multi-beat memory transactions the above described buffering of each memory address can be used to ensure that each address transfer and associated data transfer can be presented at the second interface during the same clock cycle.

"However, in one embodiment such buffering is not needed for single-beat memory transactions comprising a single address transfer and an associated single data transfer, since the data transfer can be generated internally within the same clock cycle as the address transfer.

"The memory access instructions can be store instructions or load instructions, execution of a store instruction giving rise to performance of a write transaction in order to write data from the register file to one or more specified memory addresses, whilst execution of a load instruction giving rise to a read transaction used to read data into one or more registers of the register file from one or more specified memory addresses. In one embodiment, when the memory transaction is a read transaction, the memory control circuitry is configured for at least one type of read transaction, when using the second interface, to buffer the data of each data transfer as received at the second interface within the buffer circuitry for at least one clock cycle if the register file is not available to receive that data transfer at that time, so as to allow each address transfer and associated data transfer to be presented at the second interface during the same clock cycle.

"There are a number of reasons why the register file may not be available to receive the data transfer at the time it is presented at the second interface. For example, in one embodiment, a handshake protocol that is used in association with the first interface can give rise to periods of time where the register file is unavailable. In particular, in one embodiment, a valid-ready handshake protocol is employed, and if the ready signal is not asserted in the cycle where the read data is presented at the second interface, the register file will not be able to receive that data transfer at that time, and accordingly use of the buffer enables this situation to be addressed by temporarily buffering that data transfer until such time as the register file can then receive it.

"In one embodiment, the memory control circuitry is configured to buffer the data of the data transfer as received at the second interface for at least one clock cycle if the memory transaction is a single-beat memory transaction comprising a single address transfer and an associated single data transfer. However, in one particular embodiment, such an approach is not needed for a multi-beat memory transaction, since in that particular embodiment the register file is configured to always be available to receive the data transfers of a multi-beat memory transaction.

"In one particular embodiment, when using the second interface, buffering is used for the memory address of each address transfer of a multi-beat memory transaction, and on some occasions for the read data of a single-beat read transaction. Since these buffering requirements will therefore not arise at the same time (since any particular memory transaction being processed will either be a multi-beat transaction requiring memory address buffering, or a single-beat transaction that may require read data buffering), the same physical buffer circuitry can be used to support both buffering functions, thereby providing both cost and area savings.

"The first and second interfaces can take a variety of forms. In one embodiment, the first interface is used to interface the processing circuitry with a system bus to which a number of system devices are attached. The system bus can take a variety of forms, and indeed may operate in accordance with a variety of different bus protocols. In one particular embodiment, the system bus employs the AHB bus protocol developed by ARM Limited, Cambridge, United Kingdom.

"The second interface can take a variety of forms, but in one embodiment is used to interface the processing circuitry with a general purpose input/output (GPIO) device. A dedicate I/O bus may be used to connect the second interface with the GPIO device. The protocol used over the I/O bus can be developed so as to maximise performance of the GPIO device.

"Viewed from a second aspect, the present invention provides an integrated circuit comprising: a data processing apparatus in accordance with the first aspect of the present invention; a system bus coupled to said first interface; a number of system devices attached to said system bus; and a general purpose input/output device coupled to said second interface, said general purpose input/output device providing a plurality of input/output pins for said integrated circuit.

"Viewed from a third aspect, the present invention provides a method of performing memory transactions within a data processing apparatus comprising a first interface, a second interface, and processing circuitry for executing a sequence of instructions including a memory access instruction, the method comprising: employing memory control circuitry within the processing circuitry to execute the memory access instruction to generate a memory transaction comprising at least one address transfer specifying a memory address and at least one associated data transfer specifying data to be accessed at the specified memory address; routing each address transfer and associated data transfer via the first interface when the specified memory address is within a first memory address range, and routing each address transfer and associated data transfer via the second interface when the specified memory address is within a second memory address range; when using the first interface, arranging the memory control circuitry to execute the memory access instruction so as to cause each address transfer and associated data transfer to be presented at the first interface with a first relative timing; and when using the second interface, arranging the memory control circuitry to modify execution of the memory access instruction so as to cause each address transfer and associated data transfer to be presented at the second interface with a second relative timing different to said first relative timing.

"Viewed from a fourth aspect, the present invention provides a data processing apparatus comprising: processing means for executing a sequence of instructions including a memory access instruction, the processing means including memory control means for executing said memory access instruction to generate a memory transaction comprising at least one address transfer specifying a memory address and at least one associated data transfer specifying data to be accessed at the specified memory address; first interface means and second interface means; the memory control means for routing each address transfer and associated data transfer via the first interface means when the specified memory address is within a first memory address range, and for routing each address transfer and associated data transfer via the second interface means when the specified memory address is within a second memory address range; the memory control means for executing the memory access instruction, when using the first interface means, so as to cause each address transfer and associated data transfer to be presented at the first interface means with a first relative timing; and the memory control means further for modifying execution of the memory access instruction, when using the second interface means, so as to cause each address transfer and associated data transfer to be presented at the second interface means with a second relative timing different to said first relative timing."

For more information, see this patent: Craske, Simon John. Data Processing Apparatus and Method for Performing Memory Transactions within Such a Data Processing Apparatus. U.S. Patent Number 8819378, filed November 14, 2011, and published online on August 26, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8819378.PN.&OS=PN/8819378RS=PN/8819378

Keywords for this news article include: ARM Limited, Information Technology, Information and Data Processing.

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Source: Information Technology Newsweekly


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