News Column

Patent Issued for Clock Structure with Calibration Circuitry

September 10, 2014

By a News Reporter-Staff News Editor at Journal of Engineering -- Altera Corporation (San Jose, CA) has been issued patent number 8816743, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventors are Lu, Sean Shau-Tu (San Jose, CA); Chong, Yan (San Jose, CA); Au, Kin Hong (Pulau Pinang, MY); Nguyen, Khai (San Jose, CA).

This patent was filed on January 24, 2013 and was published online on August 26, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "Integrated circuit devices, such as field-programmable gate arrays (FPGAs) and application specific integrated circuits (ASICs), may include circuits or logic blocks that can be used to perform any of a variety of functions. For example, input-output circuitry may be used to interface with external circuitry. As signals need to be transmitted to different circuit elements or blocks in an integrated circuit (IC) device, clock circuitry may be included in most IC devices to provide clock signals that may be used to synchronize the different circuit elements in the IC device.

"To ensure proper synchronization, a balanced clock structure is generally needed to minimize clock skew when the clock signals are transmitted from one block to another in the IC (e.g., from a clock source to an input-output block). Generally, multiple metal traces may be needed to route all the different clock signals with a balanced clock structure such as an H-tree clock structure.

"Input-output blocks implementing a double data rate (DDR) interface, for instance, may require up to five different clock signals (e.g., a half-rate clock and four full-rate phase-shifted clocks). Accordingly, in order to route five different clock signals through a six-layer balanced clock tree, a total of thirty (5 clock signals.times.6 clock tree layers) metal traces may be needed. These metal traces may occupy valuable space/area in the IC device.

"An unbalanced clock structure may require fewer metal traces. For instance, a fly-by clock structure may require as few as five metal traces to route five clocks. However, routing clock signals through unbalanced clock structures may potentially cause clock skew between different circuit elements or blocks on the IC device."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "Circuitry and techniques for routing and calibrating clock signals in an integrated circuit are provided. Embodiments of the present invention include circuits and techniques to route clock signals through different clock structures.

"It is appreciated that the present invention can be implemented in numerous ways, such as a process, an apparatus, a system, or a device. Several inventive embodiments of the present invention are described below.

"An integrated circuit may include a clock circuit that may be used to provide clock signals to logic circuits on the integrated circuit. For example, the clock signals may be provided to multiple input-output circuits on the integrated circuit. The integrated circuit may also include different clock structures to route the clock signals. As an example, a first clock structure may have multiple clock paths while a second clock structure may have a single clock path (e.g., a fly-by clock path that transmits the clock signals to each of the input-output circuits linearly). The clock signals generated by the clock circuit may be conveyed through the clock structures. As an example, a first subset of the clock signals may be transmitted to input-output circuits through the multiple clock paths of a first clock structure while a second subset of the clock signals may be transmitted through the fly-by clock path of a second clock structure.

"An integrated circuit may include a first clock network that may be used to convey a reference clock signal and a second clock network that may be used to convey multiple phase-shifted clock signals (e.g., clock signals that are phase-shifted from the reference clock signal). The reference clock signal and phase-shifted clock signals may be provided to logic circuits such as input-output circuits. The logic circuits may be provided with respective selection circuits that each receive the reference clock signal and the phase-shifted clock signals from the clock networks. The selection circuits may select one of the phase-shifted clock signals based on the reference clock signal. For example, the selection circuit for each input-output circuit may determine which phase-shifted clock signal matches the reference clock signal at that input-output circuit. A detection circuit may be provided for each input-output circuit along with the selection circuits. The detection circuit may be used to detect any remaining delay mismatch between the reference clock and the selected phase-shifted clock signal. The detection circuit may be used to control adjustable delay circuitry to reduce the delay mismatch between the reference clock and the selected phase-shifted clock signals.

"A method of operating circuitry on an integrated circuit includes receiving a reference clock signal from a balanced clock structure with the circuitry. Multiple clock signals may also be received with the circuitry from a fly-by clock structure. The clock signals may be phase shifted from each other. A clock signal is identified from the multiple clock signals using the circuitry. The phase of the identified clock signal may correspond to the phase of the reference clock signal."

For the URL and additional information on this patent, see: Lu, Sean Shau-Tu; Chong, Yan; Au, Kin Hong; Nguyen, Khai. Clock Structure with Calibration Circuitry. U.S. Patent Number 8816743, filed January 24, 2013, and published online on August 26, 2014. Patent URL:

Keywords for this news article include: Altera Corporation.

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Source: Journal of Engineering

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