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Researchers Submit Patent Application, "Sense Amplifier Circuit and Semiconductor Memory Device", for Approval

September 10, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors SHIN, Dong-Hak (Hwaseong-si, KR); PARK, Yong-Sang (Seooul, KR); BYUN, Young-Yong (Seoul, KR); JEONG, In-Chul (Suwon-si, KR), filed on October 22, 2013, was made available online on August 28, 2014.

The patent's assignee is Samsung Electronics Co., Ltd.

News editors obtained the following quote from the background information supplied by the inventors: "Example embodiments relate to sense amplifier circuits and semiconductor memory devices. More particularly, example embodiments relate to sense amplifier circuits in semiconductor memory devices having open bit line structures and the semiconductor memory devices.

"As an integration degree of a semiconductor memory device has increased, a cell size has been decreased, and bit line loading has been increased.

"An open bit line structure may be used to reduce the bit line loading. In the open bit line structure, a sense amplifier circuit is disposed between a pair of adjacent memory cell sub-arrays in a memory cell array, and a voltage difference between a bit line of the left memory cell sub-array and a bit line of the right memory cell sub-array is sensed by the sense amplifier circuit. Accordingly, compared with sensing a voltage difference between adjacent bit lines of the same memory cell sub-array, the open bit line structure may minimize the loading effect between the bit lines.

"However, in the open bit line structure, half of the memory cells in the leftmost or rightmost memory cell sub-array are not used, which results in the increase of the chip size. Thus, the leftmost and rightmost memory cell sub-arrays may be replaced with balance capacitors. However, even if the balance capacitors are designed to have the same loading as the bit line of the memory cell sub-array, it may be impractical for the balance capacitors to have the same distribution.

"In equalizing a pair of bit lines during a bit line pre-charge operation, the optimal target pre-charge level of the bit line pair may be VA/2, where VA is a bit line operating voltage or a bit line power supply voltage. However, if there is a loading mismatch between the bit lines, the voltage of the bit lines may not reach the optimal target pre-charge level, or VA/2. In this case, a charge sharing voltage between the bit lines may be reduced, which results in a sensing failure."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "Some example embodiments provide a sense amplifier circuit that accurately performs a sensing operation.

"According to example embodiments, a semiconductor device includes a first bit line, a second bit line, a memory cell connected to the first bit line, a bit line sense amplifier circuit, and a control circuit. The bit line sense amplifier circuit includes a first inverter having an input node coupled to a first bit line and an output node coupled to a second bit line, and a second inverter having an input node coupled to the second bit line and an output node coupled to the first bit line. The control circuit is configured to activate the first inverter without activating the second inverter during a first time period and to activate the first inverter and the second inverter at the same time during a second time period after the first time period.

"According to example embodiments, a semiconductor memory device includes a memory cell array block, n+1 sense amplifier arrays and a control circuit. The memory cell array block includes n memory cell sub-arrays, where N is an integer greater than 1. The n+1 sense amplifier arrays are located between the n memory cell sub-arrays and at first and second edges of the memory cell array block in a first direction. Each sense amplifier array includes a plurality of sense amplifier circuits. Each sense amplifier circuit includes a first inverter having an input node coupled to a first bit line and an output node coupled to a second bit line, and a second inverter having an input node coupled to the second bit line and an output node coupled to the first bit line. The control circuit is configured to generate a first sensing signal to activate first inverters of the sense amplifier circuits and a second sensing signal to activate second inverters of the sense amplifier circuits, the first sensing signal being generated prior to activating the second sensing signal.

"According to example embodiments, a method of operating a semiconductor memory device is provided. The method includes equalizing a first bit line and a second bit line; activating a first inverter including an input node coupled to the first bit line and an output node coupled to the second bit line; performing a charge sharing between one of the first and second bit lines and a memory cell connected to the one of the first and second bit lines and a first word line; and activating a second inverter including an input node coupled to the second bit line and an output node coupled to the first bit line. The charge sharing occurs between activating the first word line and activating the second inverter.

BRIEF DESCRIPTION OF THE DRAWINGS

"Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

"FIG. 1 is a block diagram illustrating a semiconductor memory device having an open bit line structure according to example embodiments.

"FIG. 2 is an exemplary circuit diagram illustrating a sense amplifier circuit according to one embodiment.

"FIG. 3 is an exemplary diagram for describing power supply voltages provided to a first inverter according to one embodiment.

"FIG. 4 is an exemplary diagram for describing power supply voltages provided to a second inverter according to one embodiment.

"FIG. 5 is an exemplary timing diagram for describing an operation of a sense amplifier circuit of FIG. 2 according to certain embodiments.

"FIG. 6 is a circuit diagram illustrating a first inverter that is in a pre-sense state.

"FIG. 7 is a timing diagram for describing a trip point level of a first inverter.

"FIG. 8 is an exemplary circuit diagram illustrating an edge sense amplifier circuit of FIG. 1 according to one embodiment.

"FIG. 9 is an exemplary circuit diagram illustrating an edge sense amplifier circuit of FIG. 1 according to another embodiment.

"FIG. 10 is a timing diagram illustrating a sensing operation of a conventional sense amplifier circuit.

"FIG. 11 is a timing diagram illustrating a sensing operation of a sense amplifier circuit according to example embodiments.

"FIG. 12 is a block diagram illustrating a semiconductor memory device according to example embodiments.

"FIG. 13 is a block diagram illustrating a memory module including a semiconductor memory device according to example embodiments.

"FIG. 14 is a block diagram illustrating a computing system including a memory module according to example embodiments."

For additional information on this patent application, see: SHIN, Dong-Hak; PARK, Yong-Sang; BYUN, Young-Yong; JEONG, In-Chul. Sense Amplifier Circuit and Semiconductor Memory Device. Filed October 22, 2013 and posted August 28, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4359&p=88&f=G&l=50&d=PG01&S1=20140821.PD.&OS=PD/20140821&RS=PD/20140821

Keywords for this news article include: Electronics, Samsung Electronics Co., Samsung Electronics Co. Ltd., Semiconductor.

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Source: Electronics Newsweekly


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