Researchers Submit Patent Application, "Light-Receiving Device, Light Receiver Using Same, and Method of Fabricating Light-Receiving Device", for Approval
The patent's assignee is
News editors obtained the following quote from the background information supplied by the inventors: "In recent years, a demand for a high-speed large-capacity (high-density) data transmission technique has been increased in a field of HPC (High Performance Computing) of high-end servers and super computers. However, in general electric transmission techniques, increase of speed and capacity has limitations and it may be difficult to realize data transmission capability (in terms of speed and a bandwidth) requested by HPC systems. As a breakthrough technique for limitation of the electric transmission techniques, an optical interconnect technique for transmitting data using light has been drawing the attention.
"A photodiode of a receiver used in a high-speed optical interconnect technique preferably has a light-receiving diameter which is formed as large as possible in terms of optical connection to an optical transmission path (an optical fiber, a polymer optical waveguide, and the like). However, a photodiode (hereinafter referred to as a 'PD' where appropriate) having a large light-receiving diameter has large capacitance in proportion to a light-receiving area, and therefore, the photodiode does not respond to a high-speed signal.
"As a method of expanding a band of such a PD having a large light-receiving diameter, peaking using an inductor has been used. An optical electric (OE) converter included in a frontend of a light receiver includes a PD which converts a component of incident light into a current and a trans-impedance amplifier (TIA) which converts a micro current generated in the PD into a voltage. However, it is difficult to form the PD and the TIA in the same process on the same substrate.
"When the PD and the TIA are connected to each other using a bonding wire, the bonding wire may be used as a peaking inductor. However, it is difficult to control an inductance of the bonding wire and speeding up has limitations. This is because, as a frequency becomes high, impedance increases, and high-frequency signals are difficult to pass.
"In the high-speed optical interconnect, PD chips and a TIA chip are connected to each other through transmission paths by flip-chip implementation. However, it is difficult to ensure physical spaces for implementing inductors corresponding to PDs in the transmission paths. Therefore, the inductors are preferably formed in the PD chips.
"Here, a technique of forming an inductor making use of a diffusion region included in a semiconductor device has been known. Related techniques are disclosed in Japanese Laid-open Patent Publication Nos. 62-244160 and 2003-179146, for example.
"In FIG. 1A, an end portion of an inductor line 102 disposed on a resistive layer 103 and an end portion of a metal line 105 connected to a transistor, are connected to an n+ type diffusion layer 104 which is formed in a semiconductor substrate 101. The n+ diffusion layer 104 enables ohmic contact between the inductor line 102 and the resistive layer 103 and ohmic contact between the metal line 105 and the resistive layer 103. In FIG. 1B, a p-type diffusion layer 205 is formed in a spiral manner in an N-well 203 included in a silicon substrate 201 so as to form an inductor, and the inductor is connected to lines 209 and 211 through via contacts 207.
"However, in a general PD process, a PIN (p-intrinsic-n) configuration is formed by epitaxial grown, and therefore, the general PD process does not include an injection process. When the methods illustrated in FIGS. 1A and 1B are employed in generation of an inductor of a PD, an injection process is additionally performed."
As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventor's summary information for this patent application: "According to an aspect of the invention, an apparatus includes a flip-chip semiconductor substrate, a light detection element configured to be formed over the flip-chip semiconductor substrate and to have a laminate structure including a first semiconductor layer of a first-conductive-type, a light-absorption layer formed over the first semiconductor layer, and a second semiconductor layer of a second-conductive-type formed over the light-absorption layer, an inductor configured to be connected to the light detection element over the flip-chip semiconductor substrate, an output electrode for bump connection configured to output a current generated by the light detection element through the inductor, a bias electrode for bump connection configured to apply a bias voltage to the light detection element through a bias electrode, and a line configured to cause a metal line of the inductor and the light detection element to be connected to the output electrode or the bias electrode.
"The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims.
"It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed.
BRIEF DESCRIPTION OF DRAWINGS
"FIG. 1A is a diagram illustrating a configuration of a general inductor using a diffusion conductive region of a semiconductor device.
"FIG. 1B is a diagram illustrating a configuration of a general inductor using a diffusion conductive region of a semiconductor device.
"FIG. 2 is a diagram illustrating a light receiver according to the present disclosure.
"FIG. 3A is a diagram illustrating a configuration of a light-receiving device designed in a process of obtaining light-receiving devices according to embodiments.
"FIG. 3B is a sectional view taken along a line IIIB of FIG. 3A.
"FIG. 3C is a sectional view taken along a line IIIC of FIG. 3A.
"FIG. 4A is a diagram illustrating a configuration of a light-receiving device according to a first embodiment.
"FIG. 4B is a sectional view taken along a line IVB of FIG. 4A.
"FIG. 4C is a sectional view taken along a line IVC of FIG. 4A.
"FIG. 5A is a diagram illustrating a method of fabricating the light-receiving device.
"FIG. 5B is a diagram illustrating the method of fabricating the light-receiving device.
"FIG. 5C is a diagram illustrating the method of fabricating the light-receiving device.
"FIG. 5D is a diagram illustrating the method of fabricating the light-receiving device.
"FIG. 6 is a graph illustrating an advantage of the light-receiving device.
"FIG. 7 is a diagram schematically illustrating a PD array chip including the light-receiving devices according to the first embodiment.
"FIG. 8 is a diagram schematically illustrating an OE converter using the PD array chip illustrated in FIG. 7.
"FIG. 9 is a diagram illustrating a PD array chip according to a second embodiment, and
"FIGS. 10A to 10C are diagrams illustrating modifications of the light-receiving device illustrated in FIGS. 4A to 4C."
For additional information on this patent application, see: Miyatake, Tetsuya. Light-Receiving Device, Light Receiver Using Same, and Method of Fabricating Light-Receiving Device. Filed
Keywords for this news article include: Data Transmission, Electronics,
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