Researchers Submit Patent Application, "Integrated Circuits and Methods for Fabricating Integrated Circuits Having Metal Gate Electrodes", for Approval
The patent's assignee is
News editors obtained the following quote from the background information supplied by the inventors: "As the critical dimensions of integrated circuits continue to shrink, the fabrication of gate electrodes for complementary metal-oxide-semiconductor (CMOS) transistors has advanced to replace silicon dioxide and polysilicon with high-k dielectric material and metal. A replacement metal gate process is often used to form the gate electrode. A typical replacement metal gate process begins by forming a sacrificial gate oxide material and a sacrificial gate between a pair of spacers on a semiconductor substrate. After further processing steps, such as an annealing process, the sacrificial gate oxide material and sacrificial gate are removed and the resulting trench is filled with a high-k dielectric and one or more metal layers. The metal layers can include workfunction metals as well as fill metals.
"Processes such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating (EP), and electroless plating (EL) may be used to deposit the one or more metal layers that form the metal gate electrode. Unfortunately, as critical dimensions decrease, issues such as trench overhang and void formation become more prevalent and pose a greater challenge to overcome. This is due to the smaller gate dimensions. Specifically, at smaller dimensions, the aspect ratio of the trench used to form the metal gate electrode becomes higher as the metal layers are deposited and form on the trench sidewalls. Metallization of high aspect ratio trenches quite often results in void formation.
"Additional issues arise with lateral scaling, for example, lateral scaling presents issues for the formation of contacts. When the contacted gate pitch is reduced to about 64 nanometers (nm), contacts cannot be formed between the gate lines while maintaining reliable electrical isolation properties between the gate line and the contact. Self-aligned contact (SAC) methodology has been developed to address this problem. Conventional SAC approaches involve recessing the replacement metal gate structure, which includes depositing both workfunction metal liners (e.g. TiN, TaN, TaC, TiC, and TiAlN) and a fill or conducting metal (e.g., W, Al, etc.), followed by a dielectric cap material deposition and chemical mechanical planarization (CMP). To set the correct workfunction for the device, thick work function metal liners may be required (e.g., a combination of different metals such as TiN, TiC, TaC, TiC, or TiAlN with a total thickness of more than 7 nm). As gate length continues to scale down, for example for sub-15 nm gates, the replacement gate structure is so narrow that it will be 'pinched-off' by the work function metal liners, leaving little or no space remaining for the lower-resistance fill metal. This will cause high resistance issue for devices with small gate lengths, and will also cause problems in the SAC replacement gate metal recess process.
"Accordingly, it is desirable to provide improved integrated circuits and methods for fabricating improved integrated circuits having metal gate electrodes. Also, it is desirable to provide methods for fabricating integrated circuits with metal gate electrodes that avoid high aspect ratios in trenches during metal deposition processes. Further, it is desirable to provide methods for fabricating integrated circuits that provide techniques for depositing metal layers in trenches that inhibit void formation. Further, it is desirable to provide methods for the fabrication of integrated circuits that integrate both metal replacement gates and self-aligned contacts with workfunction metal liner recess compatibility. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background."
As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "Integrated circuits and methods for fabricating integrated circuits are provided. In one embodiment, a method for fabricating an integrated circuit includes providing a sacrificial gate structure over a semiconductor substrate. The sacrificial gate structure includes two spacers and sacrificial gate material between the two spacers. The method recesses a portion of the sacrificial gate material between the two spacers. Upper regions of the two spacers are etched while using the sacrificial gate material as a mask. The method includes removing a remaining portion of the sacrificial gate material and exposing lower regions of the two spacers. A first metal is deposited between the lower regions of the two spacers. A second metal is deposited between the upper regions of the two spacers.
"In another embodiment, a method for fabricating an integrated circuit includes forming two spacers over a semiconductor substrate. The two spacers bound a trench having a lower portion, an upper portion, a boundary between the lower portion and the upper portion, and a top. The lower portion has a first width, the upper portion has a second width at the boundary greater than the first width, and the upper portion has an increasing width from the boundary to the top. The method includes depositing a first metal in the lower portion of the trench and depositing a second metal in the upper portion of the trench.
"In another embodiment, an integrated circuit is provided. The integrated circuit includes a semiconductor substrate and a metal gate electrode structure overlying the semiconductor substrate. The metal gate electrode structure includes a workfunction metal having a first width. The metal gate electrode structure further includes a fill metal overlying the workfunction metal and having a second width greater than the first width.
BRIEF DESCRIPTION OF THE DRAWINGS
"Embodiments of integrated circuits and methods for fabricating integrated circuits having metal gate electrodes will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and wherein:
"FIGS. 1-9 are cross-sectional side views of a portion of an integrated circuit including a first metal formed between spacers, and method steps for fabricating an integrated circuit in accordance with various embodiments herein;
"FIGS. 10-13 are cross-sectional side views of the portion of the integrated circuit of FIG. 9 in accordance with an embodiment for depositing a second metal to form a metal gate electrode; and
"FIGS. 14-17 are cross-sectional side views of the portion of the integrated circuit of FIG. 9 in accordance with another embodiment for depositing a second metal to form a metal gate electrode."
For additional information on this patent application, see: Xie, Ruilong; Park, Chanro; Ponoth, Shom. Integrated Circuits and Methods for Fabricating Integrated Circuits Having Metal Gate Electrodes. Filed
Keywords for this news article include: Electronics,
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