Researchers Submit Patent Application, "Characterization and Functional Test in a Processor Or System Utilizing Critical Path Monitor to Dynamically Manage Operational Timing Margin", for Approval
The patent's assignee is
News editors obtained the following quote from the background information supplied by the inventors: "The present invention generally relates to computer systems, and more particularly to a method of guardband testing for a system having a critical path monitor used to optimize processor frequency.
"Electronic devices such as computer systems or their components must be tested for quality control purposes to ensure that the product as shipped will function as intended. However, all testing methodologies have their limitations and can still result in mischaracterization of performance, for example, due to measurement errors, or due to process or environmental variations. In order to provide additional assurance of proper operation, designers build a safety margin into product specifications such as lower frequency or higher voltage. This additional safety margin is referred to as a guardband. The guardband thus ensures that even with testing uncertainty and worst case environment the product meets the stated minimum specifications with a high degree of confidence.
"While guardbands can guarantee proper operation under most conditions, they have several disadvantages. When guardbands are added, some devices that would have otherwise passed quality control testing will end up failing. Thus, from the standpoint of yield, the smaller the guardband the better. Guardbands can also lead to inefficient operation of the device. For example, process, voltage, and temperature variations cause timing variation within an integrated circuit design such as a microprocessor and the guardband must be such that it protects the absolute worst case that can theoretically occur, making it necessary to provide timing margins that compromise the potential performance of the device.
"In a processor core, the maximum frequency of the processor clock is dictated by the delay of a critical path within the processor, that is, a path that, at the present operating temperature and voltage, will cause the processor to fail when the frequency of the processor clock is raised above a particular limit. The critical path may be a single critical path for all operating conditions, or the critical path may change, for example, at different operating temperatures or at different voltages. Critical path monitor (CPM) circuits have been implemented that simulate the critical path or paths, and provide information regarding the critical path delay of a processor or other integrated circuit device. CPMs can synthesize critical path timing through such delay elements as wired interconnects within the IC and/or logic gates of the IC, and provide information to a phase-locked loop that generates the processor clock to provide real-time feedback of variations in the critical path delay, e.g., variation of the critical path delay with dynamic changes in the power supply voltage at particular locations within the integrated circuit device. CPMs thus allow reduction in margin (guardband) for thermal and voltage conditions in the system instead of having to always account for worst case conditions, and thereby increase operational efficiency.
"FIG. 1 illustrates the basic components for one example of a CPM circuit 2 which include a pulse generator 3, a calibration delay 4, a critical path synthesis 5, and an edge detector 6 to implement a timing-margin-to-digital conversion function. Pulse generator 3 receives a signal from the clock core and creates a timing edge synchronized to the system clock. The timing edge passes through calibration delay 4 which is used to compensate for process variation, operating point changes, and margin variation at different frequencies, and then through critical path synthesis 5 which will track with (mirror) the overall processor circuit margin. After passing through the synthesis block, the edge is latched in the edge detector by the system clock. The delay from pulse generation to edge detection is typically one clock cycle but can be multiple clock signals to improve accuracy. After the edge detector there is some signal conditioning and two output signals. An encoder 7 is used to generate a 5-bit window of the 12-bit edge detector which is then fed directly to a digital phase-lock loop (DPLL) and is used to adjust frequency to respond to changes in timing margin. The edge detector is essentially a delay line with latch elements attached at each interval. As the timing signal progresses along this delay line it flips the latch bits from 0 to 1. The location of the 1-to-0 transition that occurs when the system clock arrives marks the timing point for a given cycle. The timing margin at a given cycle is the difference between the current CPM bit position and the calibration bit position.
"Calibration of the CPM is key to ensuring proper frequency and timing margin. In this example, CPMs are calibrated by adding or subtracting calibration delay from the circuit until the DPLL achieves a target frequency at a given voltage, temperature, and workload. A valid production calibration point is found by measuring the delay of the synthesis path required to achieve the target frequency. Calibration is typically done at both ends of the intended voltage operating range. Calibration inaccuracy can occur and falls into two categories. The first is variation between the tester and the system running the same conditions and workload. The second is driven by the fact that a limited number of calibrations points (usually one) need to control the CPM through the full operational voltage range. By comparing the calibration result collected at the two voltage points the designer can measure how well the CPM tracks with the tester measured frequency. Any variation will result in divergence from the target frequency over changing voltage leading to excessive or insufficient margin."
As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "The present invention is generally directed to a method of guardband validation for an electronic device such as a processor having a monitor which controls a functional clock frequency based on current operating conditions. In an illustrative implementation, multiple calibration settings are applied to the monitor during functional operation of the processor at one or more operating points. For each calibration setting, a corresponding stress guardband is recorded. The stress guardbands result in a reduced timing margin for the processor, i.e., less than the normal operational timing margin. A desired one of the stress guardbands can later be selected for validation via subsequent guardband testing, while the monitor is active and using the calibration setting that corresponds to the selected stress guardband.
"In an implementation wherein the monitor is a critical path monitor, multiple calibration settings are based on multiple calibration delays for a critical path used by the monitor. A calibration test procedure can be used to determine the calibration delays for different operating frequencies or voltages that are set or, alternatively, the calibration delays can be set and resultant frequencies measured which are used to calculate the guardband amounts. The critical path monitor may include a modified calibration delay circuit which provides a calibrated delay signal to a critical path synthesis circuit, and the multiple calibration settings can be applied by changing delay taps of the calibration delay circuit in response to a bias delay signal from a power management controller.
"An additional innovation that can be implemented with the present invention is to use a critical path that most closely tracks the maximum operating frequency of the processor over an operating voltage range, and keeps the stress guardband between a maximum stress guardband and a minimum stress guardband, wherein the maximum stress guardband is less than a minimum nominal guardband which accounts for frequency mistracking across at least two operating points due to calibration inaccuracy.
"The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.
BRIEF DESCRIPTION OF THE DRAWINGS
"The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.
"FIG. 1 is a block diagram of a conventional critical path monitor (CPM) circuit;
"FIG. 2 is a block diagram of a computer system having one or more processors which use CPM circuits that can be recalibrated for guardband testing in accordance with one implementation of the present invention;
"FIG. 3 is a graph illustrating a curve for a maximum processor frequency (F.sub.max) as a function of voltage wherein a normal calibration based on CPM production calibration points is shifted to reduce margin in accordance with one implementation of the present invention;
"FIG. 4 is a graph depicting a multipoint calibration method for guardband testing in a system having a powersave state, a nominal state and a turbo state in accordance with one implementation of the present invention;
"FIG. 5 is a block diagram of a CPM constructed in accordance with one embodiment of the present invention wherein the delay taps used for calibration are changed to remove margin;
"FIG. 6 is a chart illustrating preferred rules for CPM calibration to achieve optimal tracking for the full guardband testing points across the operating range while keeping corresponding stress guardband testing points with desired minimum and maximum offsets;
"FIG. 7 is a chart illustrating the logical flow for a base calibration technique in accordance with a general implementation of the present invention;
"FIG. 8 is a chart illustrating the logical flow for a calibration procedure in accordance with a specific implementation of the present invention; and
"FIG. 9 is a chart illustrating the logical flow for a calibration procedure in accordance with another specific implementation of the present invention.
"The use of the same reference symbols in different drawings indicates similar or identical items."
For additional information on this patent application, see: Berry, JR., Robert W.; Drake, Alan J.;
Keywords for this news article include:
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