News Column

Researchers Submit Patent Application, "Apparatus and Method for Handling Page Protection Faults in a Computing System", for Approval

September 11, 2014



By a News Reporter-Staff News Editor at Computer Weekly News -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Murray, Simon (Manchester, GB); North, Geraint M. (Manchester, GB), filed on April 25, 2014, was made available online on August 28, 2014.

The patent's assignee is International Business Machines Corporation.

News editors obtained the following quote from the background information supplied by the inventors: "The central processing unit (CPU) or processor lies at the heart of all modern computing systems. The processor executes instructions of a computer program and thus enables the computer perform useful work. CPUs are prevalent in all forms of digital devices in modern life and not just dedicated computing machines such as personal computers, laptops and PDAs. Modern microprocessors appear in everything from automobiles to cellular telephones to children's toys.

"A problem arises in that program code which is executable by one type of processor often cannot be executed in any other type of processor, because each type of processor has its own unique Instruction Set Architecture (ISA). Hence, program code conversion has evolved to automatically convert program code written for one type of processor into code which is executable by another type of processor, or to optimise an old, inefficient piece of code into a newer, faster version for the same type of processor. That is, in both embedded and non-embedded CPUs, there are predominant ISAs for which large bodies of software already exist that could be 'accelerated' for performance or 'translated' to other processors that present better cost/performance benefits. One also finds dominant CPU architectures that are locked in time to their ISA and cannot evolve in performance or market reach. This problem applies at all levels of the computing industry, from stand-alone pocket-sized computing devices right through to massive networks having tens or hundreds of powerful servers.

"As background information in this field of program code conversion, PCT publication WO2000/22521 entitled 'Program Code Conversion', WO2004/095264 entitled 'Method and Apparatus for Performing Interpreter Optimizations during Program Code Conversion', WO2004/097631 entitled 'Improved Architecture for Generating Intermediate Representations for Program Code Conversion', WO2005/006106 entitled 'Method and Apparatus for Performing Adjustable Precision Exception Handling', and WO2006/103395 entitled 'Method and Apparatus for Precise Handling of Exceptions During Program Code Conversion', which are all incorporated herein by reference, disclose methods and apparatus to facilitate program code conversion capabilities as may be employed in the example embodiments discussed herein.

"One particular problem area concerns the handling of page protection faults. A page protection fault is a type of exception that is raised when a program tries to manipulate a memory location in a way that violates set permissions governing the types of manipulation allowed for that memory location. Typically permissions protecting memory locations are set per page of memory and hence faults generated in this way are referred to as page protection faults.

"Where the original program code (here called 'subject code') has been written according to a particular type of processor, then that subject code requires a particular type of execution environment and expects an appropriate mechanism for the handling of page protection faults. However, under program code conversion, the subject code is instead converted into target code and is executed on a target computing system. There is now a difficulty in providing an appropriate mechanism to correctly handle the page protection fault behaviour of the subject code.

"A further problem arises in that the subject code may have been written to make extensive use of a finer granularity of page protection than is supported by the native hardware are available on the target computing platform. For example, processors of the Intel.TM. x86 family support page protection for pages of sizes as small as 4096 bytes (4 kB). However, IBM.TM. PowerPC processors are often configured by the operating system to offer page protection for pages only as small as 64 kB.

"These and other problems of the prior art are addressed by the exemplary embodiments of the present invention as will be discussed in more detail below."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "According to the present invention there is provided a computer system, a computer-readable storage medium and a method as set forth in the appended claims. Other features of the invention will be apparent from the dependent claims, and the description which follows.

"The following is a summary of various aspects and advantages realizable according to embodiments of the invention. It is provided as an introduction to assist those skilled in the art to more rapidly assimilate the detailed discussion that follows and does not and is not intended in any way to limit the scope of the claims that are appended hereto.

"In particular, the inventors have developed methods directed at program code conversion. These methods are especially useful in connection with a run-time translator that provides dynamic run-time translation or acceleration of binary program code.

"In one exemplary aspect of the present invention there is provided a computing system, comprising: a translator unit arranged to convert a subject code into a target code, the subject code comprising a reference to at least one subject memory page having associated subject page access attributes; a target processor unit arranged to execute the target code; a target memory associated with the target processor unit and including a page descriptor store and plurality of memory locations related to the subject memory pages, wherein the plurality of memory locations are each associated with information in the page descriptor store according to the subject page access attributes; wherein the translator unit is arranged to allow an attempt to access a target memory location within the plurality of memory locations to proceed without an interruption in control flow, if the attempted access is within the scope of the subject page access attributes for the associated subject memory page.

"In one embodiment, the subject code is binary program code which is directly executable by a processor of a subject type.

"In one embodiment, the target code is binary program code which is directly executable by the processor unit.

"In one embodiment, translator unit is arranged to convert the subject code being binary program code which is directly executable by a processor of a first type into the target code being binary program code which is directly executable by the processor unit.

"In one embodiment, the translator unit is arranged to translate the subject code written for execution by a processor of a first type into the target code executed by the processor unit of a different, non-compatible second type.

"In one embodiment, the translator unit is arranged to optimise the subject code written for execution by a processor of a first type into the target code that is executed more efficiently by the processor unit of the same first type.

"In another aspect of the present invention there is provided a method of handling page protection faults comprising the steps of: converting a subject code executable that comprises a reference to at least one subject memory page having associated subject page access permissions into a target code executable by the at least one target processor and including references to a target memory, the conversion including establishing a page descriptor store according to the reference to the subject memory page and the associated subject page permissions; and allowing an attempt to access a target memory location within the plurality of memory locations to proceed without an interruption in control flow, if the attempted access is within the scope of the subject page access attributes for the associated subject memory page.

"In a still further aspect of the present invention there is provided a computer readable recording medium having instructions recorded thereon which when executed by a computing system having at least one target processor cause the computing system to perform at least the steps of: converting a subject code executable that comprises a reference to at least one subject memory page having associated subject page access permissions into a target code executable by the at least one target processor and including references to a target memory, the conversion including establishing a page descriptor store according to the references to the subject memory pages and the associated subject page permissions; and allowing an attempt to access a target memory location within the plurality of memory locations to proceed without an interruption in control flow, if the attempted access is within the scope of the subject page access attributes for the associated subject memory page.

"The exemplary embodiments enable detection and correct handling of page protection fault behaviour of the subject code. As a result, the computing system is now able to accurately and reliably provide subject code page protection functionality on the processor.

"Further, the exemplary embodiments discussed herein are arranged to facilitate efficient checking of subject page permissions allowing fast and efficient emulation of subject page protection behaviour. In the exemplary embodiments discussed herein, subject code which expects fine page size granularity is readily supported when converted to target code and executed on the target computing platform that supports only coarser granularity.

"The present invention also extends to a computer-readable storage medium having instructions recorded thereon which when implemented by a computer system perform any of the methods defined herein.

"At least some embodiments of the invention may be constructed, partially or wholly, using dedicated special-purpose hardware. Terms such as 'component', 'module' or 'unit' used herein may include, but are not limited to, a hardware device, such as a Field Programmable Gate Array (FPGA) or Application Specific Integrated Circuit (ASIC), which performs certain tasks. Alternatively, elements of the invention may be configured to reside on an addressable storage medium and be configured to execute on one or more processors. Thus, functional elements of the invention may in some embodiments include, by way of example, components, such as software components, object-oriented software components, class components and task components, processes, functions, attributes, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuitry, data, databases, data structures, tables, arrays, and variables. Further, although the preferred embodiments have been described with reference to the components, modules and units discussed below, such functional elements may be combined into fewer elements or separated into additional elements.

BRIEF DESCRIPTION OF THE DRAWINGS

"The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred implementations and are described as follows:

"FIG. 1 is a block diagram illustrative of apparatus wherein embodiments of the invention are applied;

"FIG. 2a is a schematic overview of a program code conversion process as employed by embodiments of the present invention;

"FIG. 2b is a schematic diagram illustrating a translator unit for use in exemplary embodiments of the present invention;

"FIG. 3 is a schematic diagram illustrating parts of an exemplary computing system relating to page protection fault handling;

"FIG. 4 is a schematic flow diagram illustrating a method of page protection fault handling according to an exemplary embodiment;

"FIG. 5 is a another schematic diagram illustrating parts of an exemplary computing system relating to page protection fault handling;

"FIGS. 6a-6e are further schematic diagrams illustrating parts of an exemplary computing system relating to page protection fault handling;

"FIGS. 7-10 are schematic diagrams illustrating still further parts of an exemplary computing system relating to page protection fault handling;

"FIGS. 11a-11e are schematic diagrams illustrating a shared redirect fault and handling thereof by an exemplary computing system; and

"FIG. 12 is a schematic diagram illustrating the path of an exception through a page protection fault handler according to an exemplary embodiment."

For additional information on this patent application, see: Murray, Simon; North, Geraint M. Apparatus and Method for Handling Page Protection Faults in a Computing System. Filed April 25, 2014 and posted August 28, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=496&p=10&f=G&l=50&d=PG01&S1=20140821.PD.&OS=PD/20140821&RS=PD/20140821

Keywords for this news article include: International Business Machines Corporation, Software.

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Source: Computer Weekly News


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