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Patent Issued for Well Region Formation Method and Semiconductor Base

September 10, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventors Yin, Haizhou (Poughkeepsie, NY); Zhu, Huilong (Poughkeepsie, NY); Luo, Zhijiong (Poughkeepsie, NY), filed on July 26, 2011, was published online on August 26, 2014.

The patent's assignee for patent number 8815698 is Institute of Microelectronics, Chinese Academy of Sciences (Beijing, CN).

News editors obtained the following quote from the background information supplied by the inventors: "Well region formation is an indispensable process in semiconductor manufacturing.

"A well region formation method I the prior art will be described with reference to the figures. The method comprises the following steps.

"As shown in FIG. 1, a semiconductor substrate 100 is provided, and the semiconductor substrate 100 comprises: a first isolation structure 111, a second isolation structure 112, a third isolation structure 113, a fourth isolation structure 114 and a fifth isolation structure 115. The isolation structures are for isolating active regions.

"As shown in FIG. 2, a photoresist 120 is formed on the semiconductor substrate 100 outside an active region that is between the second isolation structure 112 and the third isolation structure 113.

"As shown in FIG. 3, implantation of dopant ions 140 is performed.

"As shown in FIG. 4, a first well region 151 is formed in the active region between the second isolation region 112 and the third isolation structure 113, and the depth of the first well region 151 is generally greater than the depth of the isolation structures.

"As semiconductor devices are scaled further, the isolation structures continue to shrink. Therefore, in the formation of the first well region 151. because of the small size of the isolation structures, lateral scattering of some of the dopant ions occurs, i.e., some of the dopant ions pass through the second isolation structure 112 and the third isolation structure 113, forming a first inadvertently doped area 161 along the upper and middle parts of a side of the second isolation structure 112 that faces the first isolation structure 111, as well as a second inadvertently doped area 162 along the upper and middle parts of a side of the third isolation structure 113 that faces the fourth isolation structure 114; and the first inadvertently doped area 161 and the second inadvertently doped area 162 both have a doping type the same as the first well region 151.

"As shown in FIG. 5, the photoresist 120 is removed, and a semiconductor device comprising the first well region 151, the first inadvertently doped area 161 and the second inadvertently doped area 162 has been formed.

"As shown in FIG. 6, by the same method, second well regions 152 are formed in an active region between the first isolation structure 111 and the second isolation structure 112, an active region between the third isolation structure 113 and the fourth isolation structure 114, and an active region between the fourth isolation structure 114 and the fifth isolation structure 115.

"Similarly, in the formation of the second well regions 152, a third inadvertently doped area 163 is formed along the upper and middle parts of a side of the second isolation structure 112 facing the third isolation structure 113; a fourth inadvertently doped area 164 is formed along the upper and middle parts of a side of the third isolation structure 113 that faces the second isolation structure 112; a fifth inadvertently doped area 165 is formed along the upper and middle parts of a side of the fourth isolation structure 114 that faces the third isolation structure 113; and a sixth inadvertently doped area 166 is formed along the upper and middle parts of a side of the fourth isolation structure 114 that faces the fifth isolation structure 115. The third inadvertently doped area 163, the fourth inadvertently doped area 164, the fifth inadvertently doped area 165 and the sixth inadvertently doped area 166 all have a doping type the same as the second well region 152.

"The doping type of the first well region 151 is different from that of the second well region 152. For example, the first well region 151 is N-type doped and the second well region 152 is P-type doped. Then, the first inadvertently doped area 161 and the second inadvertently doped area 162 are N-type doped, and the third inadvertently doped area 163, the fourth inadvertently doped area 164. the fifth inadvertently doped area 165, and the sixth inadvertently doped area 166 are P-type doped.

"Because the fifth inadvertently doped area 165, the sixth inadvertently doped area 166 and the second well region 152 have the same doping type, the fifth inadvertently doped area 165 generally will not affect threshold voltage of the semiconductor device between the third isolation structure 113 and the fourth isolation structure 114, and the sixth inadvertently doped area 166 generally will not affect threshold voltage of the semiconductor device between the fourth isolation structure 114 and the fifth isolation structure 115.

"However, the first inadvertently doped area 161 and the second well region 152 have different doping types, hence, threshold voltage of the semiconductor device between the first isolation structure 111 and the second isolation structure 112 will change. Similarly, because the third inadvertently doped area 163 and the first well region 151 have different doping types, and the fourth inadvertently doped area 164 and the first well region 151 have different doping types, threshold voltage of the semiconductor device between the second isolation structure 112 and the third isolation structure 113 will change; because the second inadvertently doped area 162 and the second well region 152 have different doping types, threshold voltage of the semiconductor device between the third isolation structure 113 and the fourth isolation structure 114 will change. Threshold voltage change will lead to affected performance of the semiconductor device.

"Therefore, it is desired to reduce the threshold voltage change of the semiconductor device caused by lateral scattering of dopant ions in the formation of the well region."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "A problem to be solved by the present invention is to provide a well region formation method and a semiconductor base, which can remove dopant ions laterally scattered through the isolation structure, and ensure stability of the threshold voltage of the semiconductor device.

"To solve the problems above, according to the present invention, it is provided a well region formation method, comprising: forming isolation regions in a semiconductor substrate to isolate active regions; selecting at least one of the active regions, and forming a first well region in the selected active region; forming a mask to cover the selected active region, and etching the rest of the active regions, so as to form grooves; and growing a semiconductor material by epitaxy to fill the grooves.

"Optionally, the well region formation method further comprises: forming a second well region in the semiconductor material, the second well region having a doping type different from a doping type of the first well region.

"Optionally, the material of the semiconductor substrate is the same as or different from the semiconductor material.

"Optionally, the material of the semiconductor substrate and the semiconductor material both comprise Si, SiGe, SiC, or Ge.

"Optionally, if the isolation regions are defined by isolation structures, the grooves have a depth less than or equal to a depth of the isolation structures.

"To solve the problems above, according to the present invention, it is also provided a well region formation method, comprising: forming isolation regions in a semiconductor substrate for isolating active regions; forming well regions in the active regions; etching the active regions to form grooves, such that the grooves have a depth less than or equal to a depth of the well regions; and growing a semiconductor material by epitaxy to fill the grooves.

"Optionally, etching the active regions comprises: forming a mask on some of the active regions, and etching the rest of the active regions.

"Optionally, the material of the semiconductor substrate is the same as or different from the semiconductor material.

"Optionally, the well regions formed in the active regions comprise a first well region and a second well region, and the first well region and the second well region have different doping types.

"Optionally, the material of the semiconductor substrate and the semiconductor material both comprise Si. SiGe. SiC, or Ge.

"Optionally, if the isolation regions are defined by isolation structures, the grooves have a depth less than or equal to a depth of the isolation structures.

"To solve the problems above, according to the present invention, it is also provided a semiconductor base, comprising: a semiconductor substrate, which comprises an isolation structure for isolating at least two active regions; a modified semiconductor region, wherein the modified semiconductor region is embedded in at least some of the active regions, the material of the modified semiconductor region is different from the material of the semiconductor substrate, and an upper surface of the modified semiconductor region is at least even with an upper surface of the active regions.

"Optionally, a lower surface of the modified semiconductor region is higher than a lower surface of the isolation structure.

"Optionally, the material of the semiconductor substrate comprises Si, SiGe, SiC, or Ge.

"Optionally, the material of the modified semiconductor region comprises Si, SiGe, SiC, or Ge.

"In comparison with the prior art, the present invention has following advantages.

"1) According to an embodiment of the present invention, after a well region is formed in an active region, a mask is formed to cover the active region, and the semiconductor substrate containing inadvertently doped areas is removed, then, a semiconductor substrate without inadvertently doped areas is grown, thereby avoiding threshold voltage change of the semiconductor device caused by the inadvertently doped areas, and ensuring stability of the threshold voltage of the semiconductor device.

"2) According to another embodiment of the present invention, after well regions are formed in active regions, the semiconductor substrate containing inadvertently doped areas is removed, without damaging the well regions, then, a semiconductor substrate without inadvertently doped areas is grown, thereby avoiding threshold voltage change of the semiconductor device caused by the inadvertently doped areas, and ensuring stability of the threshold voltage of the semiconductor device.

"3) According to the present invention, it is also provided a semiconductor base, comprising a semiconductor substrate and a modified semiconductor region with different doping types. Because the semiconductor base has less or none of the inadvertently doped areas, stability oldie threshold voltage of the eventual semiconductor device can be ensured."

For additional information on this patent, see: Yin, Haizhou; Zhu, Huilong; Luo, Zhijiong. Well Region Formation Method and Semiconductor Base. U.S. Patent Number 8815698, filed July 26, 2011, and published online on August 26, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8815698.PN.&OS=PN/8815698RS=PN/8815698

Keywords for this news article include: Chinese Academy of Sciences, Electronics, Institute of Microelectronics, Institute of Microelectronics Chinese Academy of Sciences, Microelectronics, Semiconductor.

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Source: Electronics Newsweekly


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