Patent number 8815718 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "This invention relates to the fabrication of semiconductor devices. More particularly, the present invention relates to a method for fabricating vertical surround gate structures in a semiconductor device array.
"In semiconductor device applications, conventional planar transistors have the most mature integration process. However, in memory applications, particularly access devices (or selectors), reduction of device footprint is essential to improve memory density. Planar transistor performance is generally restricted by channel width and length. Reducing channel width or length can improve memory density at the cost of degraded device performance.
"Vertical surround gate devices have become an attractive design choice for memory applications. In vertical surround gate devices the current flow is oriented in a vertical direction, providing many advantages to area efficiency. However, many current integration processes for vertical surround gate structures are not easily compatible with standard CMOS integration. Specifically, many current applications of double patterning techniques for channel, source, and drain formation are disruptive to the standard CMOS thermal cycle. Additionally, from a cost efficient perspective, it is desirable to integrate the vertical surround gate structures with a minimum number of additional masks."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "An aspect of the invention is a method for fabricating vertical surround gate structures in a semiconductor device array such that the processes are compatible with standard CMOS fabrication processes. The semiconductor device array structure includes a CMOS region and an array region. The method includes successively forming a polish stop layer, a plurality of patterning layers, and a CMOS layer over a substrate. The method also includes forming a plurality of array pillars and array trenches such that forming the array pillars and trenches includes removing the CMOS cover layer and patterning layers. The method includes planarizing the polish stop layer. The method also includes doping portions of the substrate within the array trenches. Furthermore, the method includes forming a plurality of vertical surround gates around the array pillars and within the array trenches. The method also includes forming an array filler layer to fill in the array trenches. The method includes forming a CMOS photoresist pattern over the array filler layer. The method also includes etching CMOS trenches in the CMOS photoresist pattern down through a portion of the substrate. The etch also forming a plurality of contact holes in a portion of the substrate."
URL and more information on this patent, see: Lam, Chung H.; Li, Jing. Vertical Surround Gate Formation Compatible with CMOS Integration. U.S. Patent Number 8815718, filed
Keywords for this news article include: Electronics,
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