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Patent Issued for Semiconductor Package Having a Contamination Preventing Layer Formed in the Semiconductor Chip

September 10, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- SK Hynix Inc. (Gyeonggi-do, KR) has been issued patent number 8816477, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventor is Son, Ho Young (Chungcheongbuk-Do, KR).

This patent was filed on August 15, 2012 and was published online on August 26, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "The present invention relates to a semiconductor package, and more particularly, to a semiconductor package which can prevent diffusion of copper into a semiconductor chip and a method for manufacturing the same.

"Recently, in order to improve data storage capacity and is data processing speeds of semiconductor packages, stack semiconductor packages comprising at least two stacked semiconductor chips have been developed using various structures.

"The semiconductor chips of the stack type semiconductor package are electrically connected with one another, for example, by through electrodes which are formed to pass through the respective semiconductor chips.

"However, in the stack type semiconductor package realized by connecting through electrodes, when forming bump pads on the back surface of each semiconductor chip, if the applied state of a barrier layer or an adhesive layer is poor, a problem is caused in that copper (Cu) of a copper seed layer and a copper plating layer is likely to diffuse into the semiconductor chip through the interface between a dielectric layer formed on the back surface of the semiconductor chip and the through electrodes.

"Copper diffusion easily occurs not only in a process for forming the bump pads but also from copper which is pushed outward from the through electrodes exposed when grinding the back surface of the semiconductor chip.

"Specifically, because copper may diffuse up to the circuit unit of the semiconductor chip and may cause malfunction of the circuit unit, reliability of the semiconductor package is degraded."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventor's summary information for this patent: "An embodiment of the present invention is directed to a semiconductor package which can prevent copper (Cu) used in manufacturing of a semiconductor package from diffusing into a semiconductor chip.

"Also, an embodiment of the present invention is directed to a method for manufacturing the semiconductor package.

"Further, embodiments of the present invention are directed to a semiconductor module and an information processing system using the semiconductor package.

"In one embodiment of the present invention, a semiconductor package includes: a semiconductor chip having a front surface and a back surface facing away from the front surface; a through electrode formed in the semiconductor chip and passing through the front surface and the back surface; and a contamination preventing layer formed in the semiconductor chip, the through electrode passing through the contamination preventing layer.

"The contamination preventing layer may be an impurity layer including argon (Ar).

"The contamination preventing layer may be disposed at a depth of 1.about.10 .mu.m from the back surface of the semiconductor chip such that the contamination preventing layer is closer to the back surface than the front surface of the semiconductor chip.

"The semiconductor package may further include an is isolation pattern formed on the back surface of the semiconductor chip into a shape which surrounds the through electrode.

"The isolation pattern may be a groove which is defined by etching a portion of the back surface of the semiconductor chip between adjacent through electrodes and on the contamination preventing layer.

"The isolation pattern may have the shape of a closed loop or a polygon when viewed from the top.

"The semiconductor package may further include a back side bump formed on one end of the through electrode which is disposed on the back surface of the semiconductor chip.

"The semiconductor package may further include a dielectric layer formed between the back surface of the semiconductor chip and the back side bump.

"The semiconductor package may further include a front side electrode formed on an one end of the through electrode which is disposed on the front surface of the semiconductor chip.

"In another embodiment of the present invention, a method for manufacturing a semiconductor package includes: preparing a semiconductor chip which has a front surface and a back surface facing away from the front surface; forming a contamination preventing layer in the semiconductor chip; forming a through electrode from the front surface of the semiconductor chip to a depth that passes through the contamination preventing layer; and is removing a portion of the back surface of the semiconductor chip to expose the through electrode.

"The contamination preventing layer may be formed by implanting impurities including argon (Ar).

"The through electrode may be formed to have a depth deeper by 1.about.10 .mu.m than the contamination preventing layer when measured from the front surface of the semiconductor chip.

"After the removing of the portion of the back surface of the semiconductor chip, the method may further include forming an isolation pattern which surrounds each through electrode, by etching the back surface of the semiconductor chip to expose the contamination preventing layer.

"After the removing of the portion of the back surface of the semiconductor chip, the method may further include forming a dielectric layer on the back surface of the semiconductor chip; and forming an isolation pattern which surrounds each through electrode, by etching the dielectric layer and the back surface of the semiconductor chip to expose the through electrode and the contamination preventing layer.

"The isolation pattern may be formed to have a shape of a closed loop or a polygon when viewed from the top.

"After the forming of the isolation pattern, the method may further include forming a back side bumpon an other end of the through electrode which is disposed on the back surface of the is semiconductor chip.

"The method may further include forming a front electrode on an one end of the through electrode which is disposed on the portion of the front surface of the semiconductor chip."

For the URL and additional information on this patent, see: Son, Ho Young. Semiconductor Package Having a Contamination Preventing Layer Formed in the Semiconductor Chip. U.S. Patent Number 8816477, filed August 15, 2012, and published online on August 26, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8816477.PN.&OS=PN/8816477RS=PN/8816477

Keywords for this news article include: Electronics, SK Hynix Inc., Semiconductor.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


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Source: Electronics Newsweekly


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