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Patent Issued for Semiconductor Package and Method of Fabricating the Same

September 10, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent by the inventors Kim, Young Lyong (Anyang-si, KR); Kim, Hyeongseob (Cheonan-si, KR); Lee, Jongho (Hwaseong-si, KR); Ahn, Eunchul (Yongin-si, KR), filed on July 1, 2011, was published online on August 26, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8815731 is assigned to SAMSUNG Electronics Co., Ltd. (Suwon-si, KR).

The following quote was obtained by the news editors from the background information supplied by the inventors: "The present general inventive concept relates semiconductor packages and methods of fabricating the same and, more particularly, to a flip chip package and a method of fabricating the same.

"A flip chip package is a type of semiconductor chip package. A flip chip package includes a semiconductor chip and a printed circuit board (PCB) that are disposed to face each other. Pads of the semiconductor chip and pads of the PCB are electrically connected in one-to-one correspondence by a conductive pump. As a distance between a semiconductor chip and a PCB becomes shorter and shorter, a conductive bump continues to decrease in size. The decreased size of the conductive bump results in formation of voids and seams in a filler material that fills a space between the semiconductor chip and the PCB."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "Exemplary embodiments of the present general inventive concept can provide a semiconductor package. The semiconductor package may include a first substrate including a first pad, a second substrate spaced apart from the first substrate and where a second pad is formed to face the first pad, a first bump disposed to electrically connect the first pad to the second pad, and a second bump disposed between the first substrate and the second substrate. A coefficient of thermal expansion (CTE) of the second bump may be smaller (e.g., substantially smaller) than that of the first bump.

"Additional features and utilities of the present general inventive concept will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the general inventive concept.

"In exemplary embodiments of the present general inventive concept, the second bump may connect to a first edge of the first substrate to a second edge of the second substrate.

"According to exemplary embodiments of the present general inventive concept, the second bump may mechanically connect a first portion of the first substrate where the first pad is not formed to a second portion of a second substrate where the second pad is not formed.

"According to exemplary embodiments of the present general inventive concept, the first bump may include a first conductive pattern formed adjacent to the first pad and a second conductive pattern having one side in contact with the first conductive pattern and another side in contact with the second conductive pattern.

"According to exemplary embodiments of the present general inventive concept, the first conductive pattern may include copper (Cu) and the second conductive pattern may include a solder ball.

"According to exemplary embodiments of the present general inventive concept, the second bump may include a third conductive pattern that is in contact with the first substrate and a fourth conductive pattern having one side is in contact with the third conductive pattern and another side in contact with the second substrate.

"According to exemplary embodiments of the present general inventive concept, the third conductive pattern may include copper (Cu) and the fourth conductive pattern may include a solder ball.

"According to exemplary embodiments of the present general inventive concept, the second substrate may include a first opening exposing the second pad and a second opening partially exposing the second substrate. A portion of the first bump may be buried in the first opening, and a portion of the second bump may be buried in the second opening.

"According to exemplary embodiments of the present general inventive concept, the semiconductor package may further include a filler material filling a space between the first substrate and the second substrate.

"According to exemplary embodiments of the present general inventive concept, the filler material may include an epoxy resin and a filler.

"Exemplary embodiments of the present general inventive concept may also provide a method of fabricating a semiconductor package. The method may include forming a first pad at one side of a first substrate, forming a first bump to be electrically connected to the first pad, forming a second bump at one face of the first substrate where the first pad is not formed, forming a second pad at one face of a second substrate, electrically connecting the first bump to the second pad, and mechanically connecting the second bump to the one face of the second substrate where the second pad is not formed. A coefficient of thermal expansion (CTE) of the second bump may be smaller (e.g., substantially smaller) than that of the first bump.

"According to exemplary embodiments of the present general inventive concept, the forming of the first bump may include partially etching the first substrate to expose the first pad, forming a first conductive pattern to be electrically connected to the first pad, and forming a second conductive pattern on the first conductive pattern to be electrically connected to the first conductive pattern.

"According to exemplary embodiments of the present general inventive concept, the forming of the second bump may include forming a third conductive pattern on the second substrate and forming a fourth conductive pattern on the third conductive pattern.

"According to exemplary embodiments of the present general inventive concept, the third conductive pattern may be formed together with the first conductive pattern, and the fourth conductive pattern may be formed together with the second conductive pattern.

"According to exemplary embodiments of the present general inventive concept, the electrically connecting of the first bump to the second pad may include partially etching the second substrate such that a first opening is formed to expose the second pad, inserting the first bump into the first opening, and electrically connecting the first bump to the second bump.

"According to exemplary embodiments of the present general inventive concept, the connecting of the second bump to the second substrate may include partially etching the second substrate to form a second opening, inserting the second bump into the second opening, and connecting the second bump to the second substrate.

"According to exemplary embodiments of the present general inventive concept, the first opening may be together with the second opening. The first bump and the second bump may be inserted into the first opening and the second opening.

"Exemplary embodiments of the present general inventive concept may also provide a semiconductor package including a first substrate, a second substrate spaced apart from the first substrate, a first bump disposed to electrically connect a first pad of the first substrate to a second pad of the second substrate, and a second bump to mechanically connect a first edge of the first substrate to a second edge of the second substrate, where a coefficient of thermal expansion (CTE) of the second bump is smaller than that of the first bump.

"The second substrate of the semiconductor package can include a first opening to expose the second pad of the second substrate, and a second opening to at least partially expose the second substrate.

"The semiconductor package can include where the second bump mechanically connects the at least partially exposed second substrate with a portion of the first substrate that is spaced apart from the first pad.

"The semiconductor package can include where the first substrate includes an insulating layer, and a recess in the insulating layer to at least partially expose the first pad.

"Exemplary embodiments of the present general inventive concept may also include an electronic apparatus including a memory card having a memory controller communicatively coupled to a memory device, the memory card including a first substrate, a second substrate spaced apart from the first substrate, a first bump disposed to electrically connect a first pad of the first substrate to a second pad of the second substrate, a second bump to mechanically connect a first edge of the first substrate to a second edge of the second substrate, where a coefficient of thermal expansion (CTE) of the second bump is smaller than that of the first bump, and where the memory controller and the memory device are disposed on at least one of the first substrate and the second substrate.

"Exemplary embodiments of the present general inventive concept may also include an electronic apparatus, including an information processing system including a processor communicatively coupled to a memory system having a memory controller and a memory device, the information processing system including a first substrate, a second substrate spaced apart from the first substrate, a first bump disposed to electrically connect a first pad of the first substrate to a second pad of the second substrate, and a second bump to mechanically connect a first edge of the first substrate to a second edge of the second substrate, where a coefficient of thermal expansion (CTE) of the second bump is smaller than that of the first bump, and where the information processing system including the processor and the memory system are disposed on at least one of the first substrate and the second substrate."

URL and more information on this patent, see: Kim, Young Lyong; Kim, Hyeongseob; Lee, Jongho; Ahn, Eunchul. Semiconductor Package and Method of Fabricating the Same. U.S. Patent Number 8815731, filed July 1, 2011, and published online on August 26, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8815731.PN.&OS=PN/8815731RS=PN/8815731

Keywords for this news article include: Electronics, SAMSUNG Electronics Co., SAMSUNG Electronics Co. Ltd., Semiconductor.

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Source: Electronics Newsweekly


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