News Column

Patent Issued for Point to Multi-Point Clock-Forwarded Signaling for Large Displays

September 10, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventors Amirkhany, Amir (Sunnyvale, CA); Jaffari, Nasrin (Sunnyvale, CA), filed on February 13, 2014, was published online on August 26, 2014.

The patent's assignee for patent number 8817184 is Samsung Display Co., Ltd. (Yongin, KR).

News editors obtained the following quote from the background information supplied by the inventors: "In some digital displays such as televisions, data must be transmitted within the display panel, e.g., display data may be transmitted from a timing controller on a printed circuit board (PCB) behind the display panel to driver integrated circuits (ICs) on the display panel. In such an implementation, each driver IC requires a clock signal, i.e., a receiver clock, which may also be referred to as a sampling clock, to sample the received data.

"A sampling clock may be extracted, by the driver IC, from the transitions embedded in the data sequence, a process that may require a clock and data recovery circuit (CDR) at the receiver, and a form of transition encoding on the transmitted data, to insure that transitions in the received data are sufficiently frequent. In another kind of implementation, the driver ICs receive a low-frequency clock from the transmitter, and use a phase-locked loop (PLL) to multiply the clock frequency to the required rate for sampling the received data.

"Transmitter clock jitter may result in irregularity in the timing of transitions in the transmitted data. It may also result in irregularity in the timing of edges in the transmitted clock, if a clock is transmitted. In CDR-based or PLL-based receivers, due to inherent low-pass filtering in the CDR or PLL, the correlation between high-frequency clock jitter and data jitter may be significantly reduced. This may result in changes in timing margin, as illustrated in FIG. 1A, in which timing margin is defined as the time interval between a clock edge and the subsequent transition in the received data. Such changes in timing margin may limit the maximum data rates achievable with acceptably low error rates. If, on the other hand, the receiver clock jitter were fully correlated with the received data's jitter, the effects of timing jitter would be cancelled.

"An intra-panel interface, e.g., the interface between a timing controller (TCON) and driver ICs in a display may be asymmetric in the sense that the receivers, i.e., the driver ICs, are noisy, because they include high-voltage display column drivers, and the driver ICs are slow, because they are fabricated in a high-voltage process, while the transmitter, i.e., the TCON, is fabricated in a standard process with standard voltages, and is therefore quieter and faster. As a result it is desirable to place precision circuitry in the transmitter rather than in the receiver, when possible.

"Thus, there is a need for a system and method for providing a clock signal to several receivers which preserves the correlation between clock jitter and data jitter, and which is implemented primarily in the transmitter."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "In one embodiment of a system for forwarding a sample rate clock along with data, a sample rate clock is sent by a transmitter, along with data, to one or more receivers. The receivers sample the received data using the received sampling clock. Delay adjust circuits in the transmitter adjust the delay of each transmitted data stream using delay error sensing and correction implemented in a back channel between the receivers and the transmitter.

"According to an embodiment of the present invention there is provided a system for transmitting data, the system including: a transmitter including: a plurality of data output circuits, each of the plurality of data output circuits including a delay adjust circuit, the plurality of data output circuits being configured to operate at a data rate; and a sampling clock output circuit configured to output a sampling clock signal with a total sampling clock edge rate equal to the data rate, and a plurality of receivers, each of the plurality of receivers connected to a corresponding one of the plurality of data output circuits, each of the plurality of receivers including: a sampling clock input connected to the sampling clock output circuit; a data input circuit; and a receiver output, a back channel connected to a receiver of the plurality of receivers, and to the delay adjust circuit of the corresponding data output circuit, the back channel configured to: measure a delay error in the receiver; and adjust a delay in the delay adjust circuit of the corresponding data output circuit, to reduce the delay error.

"In one embodiment, the delay adjust circuit is configured to be controlled by a digital signal.

"In one embodiment, the system is configured to perform a sweep calibration to set the delay in the delay adjust circuit.

"In one embodiment, the sweep calibration includes: sending, by the plurality of data output circuits, a sequence of alternating ones and zeros; operating the receiver in a mode in which every other sampling clock edge is disregarded; changing the delay in the delay adjust circuit in increments in a first direction until both, at a first threshold delay, a first pass-fail or fail-pass boundary is reached, and, at a second threshold delay, a second pass-fail or fail-pass boundary is reached; determining, from the first threshold delay and from the second threshold delay, a range of delays corresponding to a pass region; and setting the delay of the delay adjust circuit to a value that is substantially centered in the pass region.

"In one embodiment, the system is configured to perform an incremental delay adjustment, starting from an initial delay value.

"In one embodiment, the back channel includes a transition detector.

"In one embodiment, the incremental delay adjustment includes: sending, by the plurality of data output circuits, a sequence of alternating ones and zeros; operating the receiver in a mode in which every other sampling clock edge is disregarded; increasing the delay, in a first trial delay adjustment, to a value exceeding the initial delay value by an amount corresponding to 90 degrees of sampling clock phase; decreasing the delay, in a second trial delay adjustment, to a value less than the initial delay value by an amount corresponding to 90 degrees of sampling clock phase; setting the delay in the delay adjust circuit to a value exceeding the initial value by an increment when the second trial delay adjustment resulted in a transition at the receiver output; and setting the delay in the delay adjust circuit to a value less than the initial delay value by the increment when the first trial delay adjustment resulted in a transition at the receiver output.

"In one embodiment, each of the plurality of receivers includes a crossing clock circuit configured to generate a crossing clock signal having a total crossing clock edge rate equal to the total sampling clock edge rate and offset 90 degrees in phase from the sampling clock signal; and the back channel is configured to measure the delay error in the receiver by determining whether an edge of the crossing clock occurs before or after a transition in a signal received at the data input circuit.

"In one embodiment, the receiver includes a clocked comparator.

"In one embodiment, the sampling clock inputs of the plurality of receivers are connected to the sampling clock output circuit by a sampling clock splitting tree.

"In one embodiment, the sampling clock splitting tree includes a plurality of transmission line splitters, each of the plurality of transmission line splitters having an input at a first characteristic impedance and two outputs at a second characteristic impedance, the second characteristic impedance being twice the first characteristic impedance.

"In one embodiment, the sampling clock inputs of the plurality of receivers are connected to the sampling clock output circuit by a fly-by architecture.

"In one embodiment, the system includes a plurality of inductors, each of the plurality of inductors connected to a sampling clock input of the plurality of receivers.

"In one embodiment, the delay adjust circuit of the corresponding data output circuit is a variable delay line.

"In one embodiment, the delay adjust circuit of the corresponding data output circuit is a phase interpolator.

"In one embodiment, the sampling clock output circuit includes a phase locked loop.

"In one embodiment, the back channel includes a plurality of multiplexers, each of the plurality of multiplexers connected to one of the plurality of receivers.

"In one embodiment, the back channel includes a plurality of delay control outputs, each of the delay control outputs connected to one of the delay adjust circuits of the plurality of data output circuits.

"In one embodiment, the delay control outputs are digital delay control outputs.

"In one embodiment, a video display includes the system, and the system is configured to perform a periodic incremental delay adjustment, starting from an initial delay value and wherein the system is configured to perform the periodic incremental delay adjustment during a blanking interval of the video display."

For additional information on this patent, see: Amirkhany, Amir; Jaffari, Nasrin. Point to Multi-Point Clock-Forwarded Signaling for Large Displays. U.S. Patent Number 8817184, filed February 13, 2014, and published online on August 26, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8817184.PN.&OS=PN/8817184RS=PN/8817184

Keywords for this news article include: Electronics, High Voltage, Samsung Display Co., Samsung Display Co. Ltd.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


For more stories covering the world of technology, please see HispanicBusiness' Tech Channel



Source: Electronics Newsweekly


Story Tools






HispanicBusiness.com Facebook Linkedin Twitter RSS Feed Email Alerts & Newsletters