News Column

Patent Issued for Nonvolatile Memory Devices and Methods of Forming the Same

September 10, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Jeong, Yongsik (Suwon-si, KR); Han, Jeonguk (Suwon-si, KR); Park, Weonho (Hwaseong-si, KR); Shim, Byungsup (Yongin-si, KR), filed on November 16, 2012, was published online on August 26, 2014.

The assignee for this patent, patent number 8815681, is Samsung Electronics Co., Ltd. (Gyeonggi-do, KR).

Reporters obtained the following quote from the background information supplied by the inventors: "Example embodiments disclosed herein relate to semiconductor devices and methods of forming the same. Other example embodiments relate to nonvolatile memory devices and methods of forming the same.

"As the integration of a semiconductor device increases, the width of patterns and spaces between the patterns are reduced. A reduction in the width of patterns, or in the spaces between the patterns, results in an increase in the costs associated with manufacturing a semiconductor device. Exposure equipment that uses a corresponding short wavelength may be necessary to form a pattern having a reduced line width. However, exposure equipment that produces a pattern having a reduced line width is costly, thereby increasing the costs associated with manufacturing the semiconductor device.

"A reduction in the width of the patterns and the spaces of the patterns causes a variety of difficulties in manufacturing a semiconductor device. For example, a reduction in the space between gate patterns makes it difficult to form a source plug and a drain plug connected to a source electrode and a drain electrode, respectively, of a transistor. Because a bit line is formed to cross a source line, the bit line is not formed on the same layer as the source line. And, at least one of the bit line and the source line is connected to a drain electrode or a source electrode through plugs. In this case, a space between the gate patterns should be formed wide enough to prevent (or reduce the likelihood of) a short between a plug and a gate electrode. The necessity of wide space hinders the ability to form a more integrated semiconductor device.

"In the case of a conventional NOR-type flash memory device, because the source electrodes are connected to one another through a buried source line, the number of source plugs may be reduced. Because the drain electrodes of cells are connected to a bit line through drain plugs, a NOR-type flash memory device has a lower degree of integration than a NAND-type flash memory device.

"Methods that reduce the number of drain plugs have been studied."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "Example embodiments disclosed herein relate to semiconductor devices and methods of forming the same. Other example embodiments relate to nonvolatile memory devices and methods of forming the same.

"Example embodiments provide a nonvolatile memory device including first regions and second regions extending in a first direction. The first and second regions may be alternately disposed in a semiconductor substrate along a second direction crossing the first direction. The nonvolatile memory device includes buried doped lines formed at the first regions respectively and extending in the first direction. The buried doped lines may be doped with a dopant of a first conductivity type. The non-volatile memory device includes bulk regions doped with a dopant of a second conductivity type and device isolation patterns disposed along the second direction. The bulk regions and the device isolation patterns may be formed in the second regions. Word lines crossing the buried doped lines and the bulk regions may be formed parallel to one another. Contact structures may be connected to the buried doped lines and disposed between the device isolation patterns.

"Other example embodiments provide a method of forming a nonvolatile memory device. The method may include providing a semiconductor substrate including first regions and second regions extended in a first direction. The first and second regions may be alternately disposed along a second direction crossing the first direction. Bulk regions doped with a dopant of a second conductivity type, and device isolation patterns, may be formed disposed along a second direction crossing the first direction. The bulk regions and the device isolation patterns may be formed in the second regions. Buried doped lines may be formed at the first regions respectively and extend in the first direction. The buried doped lines may be doped with a dopant of a first conductivity type. Word lines crossing the buried doped lines and the bulk regions may be formed parallel to one another. Contact structures may be connected to the buried doped lines between the device isolation patterns."

For more information, see this patent: Jeong, Yongsik; Han, Jeonguk; Park, Weonho; Shim, Byungsup. Nonvolatile Memory Devices and Methods of Forming the Same. U.S. Patent Number 8815681, filed November 16, 2012, and published online on August 26, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8815681.PN.&OS=PN/8815681RS=PN/8815681

Keywords for this news article include: Electronics, Samsung Electronics Co., Samsung Electronics Co. Ltd., Semiconductor.

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Source: Electronics Newsweekly


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