News Column

Patent Issued for Multilayer Electronic Structures with Vias Having Different Dimensions

September 9, 2014



By a News Reporter-Staff News Editor at Journal of Technology -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventor Hurwitz, Dror (Zhuhai, CN), filed on May 29, 2012, was published online on August 26, 2014.

The assignee for this patent, patent number 8816218, is Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. (Zhuhai, CN).

Reporters obtained the following quote from the background information supplied by the inventors: "The present invention is directed to multilayer interconnect structures including novel vias having different shapes and sizes.

"Driven by an ever greater demand for miniaturization of ever more complex electronic components, consumer electronics such as computing and telecommunication devices are becoming more integrated. This has created a need for support structures such as IC substrates and IC interposers that have a high density of multiple conductive layers and vias that are electrically insulated from each other by a dielectric material.

"The general requirement for such support structures is reliability and appropriate electrical performance, thinness, stiffness, planarity, good heat dissipation and a competitive unit price.

"Of the various approaches for achieving these requirements, one widely implemented manufacturing technique that creates interconnecting vias between layers uses lasers to drill holes through the subsequently laid down dielectric substrate through to the latest metal layer for subsequent filling with a metal, usually copper, that is deposited therein by a plating technique. This approach to creating vias is sometimes referred to as `drill & fill`, and the vias created thereby may be referred to as `drilled & filled vias`.

"There are a number of disadvantages with the drilled & filled via approach. Since each via is required to be separately drilled, the throughput rate is limited, and the costs of fabricating sophisticated, multi-via IC substrates and interposers becomes prohibitive. In large arrays it is difficult to produce a high density of high quality vias having different sizes and shapes in close proximity to each other by the drill & fill methodology. Furthermore, laser drilled vias have rough sides walls and taper inwards through the thickness of the dielectric material. This tapering reduces the effective diameter of the via. It may also adversely affect the electrical contact to the previous conductive metal layer especially at ultra small via diameters, thereby causing reliability issues. Additionally, the side walls are particularly rough where the dielectric being drilled is a composite material comprising glass or ceramic fibers in a polymer matrix, and this roughness may create additional stray inductances.

"The filling process of the drilled via holes is usually achieved by copper electroplating. The electroplating deposition technique may result in dimpling, where a small crater appears at the top of the via. Alternatively, overfill may result, where a via channel is filled with more copper than it can hold, and a domed upper surface that protrudes over the surrounding material is created. Both dimpling and overfill tend to create difficulties when subsequently stacking vias one on top of the other, as required when fabricating high-density substrates and interposers. Furthermore, it will be appreciated that large via channels are difficult to fill uniformly, especially when they are in proximity to smaller vias within the same interconnecting layer of the interposer or IC substrate design.

"Although the range of acceptable sizes and reliability is improving over time, the disadvantages described hereinabove are intrinsic to the drill & fill technology and are expected to limit the range of possible via sizes. It will further be noted that laser drilling is best for creating round via channels. Although slot shaped via channels may theoretically be fabricated by laser milling, in practice, the range of geometries that may be fabricated is somewhat limited and vias in a given support structure are typically cylindrical and substantially identical.

"Fabrication of vias by drill & fill is expensive and it is difficult to evenly and consistently fill the via channels created thereby with copper using the relatively, cost-effective electroplating process.

"Laser drilled vias in composite dielectric materials are practically limited to 60.times.10.sup.-6 m diameter, and even so suffer from significant tapering shape as well as rough side walls due to the nature of the composite material drilled, in consequence of the ablation process involved.

"In addition to the other limitations of laser drilling as described hereinabove, there is a further limitation of the drill & fill technology in that it is difficult to create different diameter vias in the same layer, since when drill different sized via channels are drilled and then filled with metal to fabricate different sized vias, the via channels fill up at different rates. Consequently, the typical problems of dimpling or overfill that characterize drill & fill technology are exasperated, since it is impossible to simultaneously optimize deposition techniques for different sized vias.

"An alternative solution that overcomes many of the disadvantages of the drill & fill approach, is to fabricate vias by depositing copper or other metal into a pattern created in a photo-resist, using a technology otherwise known as `pattern plating`.

"In pattern plating, a seed layer is first deposited. Then a layer of photo-resist is deposited thereover and subsequently exposed to create a pattern, and selectively removed to make trenches that expose the seed layer. Via posts are created by depositing Copper into the photo-resist trenches. The remaining photo-resist is then removed, the seed layer is etched away, and a dielectric material that is typically a polymer impregnated glass fiber mat, is laminated thereover and therearound to encase the vias posts. Various techniques and processes can be then use to planarize the dielectric material, removing part of it to expose the tops of the via posts to allow conductive connection to ground thereby, for building up the next metal layer thereupon. Subsequent layers of metal conductors and via posts may be deposited there onto by repeating the process to build up a desired multilayer structure.

"In an alternative but closely linked technology, known hereinafter as `panel plating`, a continuous layer of metal or alloy is deposited onto a substrate. A layer of photo-resist is deposited on top of the substrate, and a pattern is developed therein. The pattern of developed photo-resist is stripped away, selectively exposing the metal thereunder, which may then be etched away. The undeveloped photo-resist protects the underlying metal from being etched away, and leaves a pattern of upstanding features and vias.

"After stripping away the undeveloped photo-resist, a dielectric material, such as a polymer impregnated glass fiber mat, may be laminated around and over the upstanding copper features and/or via posts. After planarizing, subsequent layers of metal conductors and via posts may be deposited there onto by repeating the process to build up a desired multilayer structure.

"The via layers created by pattern plating or panel plating methodologies described above are typically known as `via posts` and feature layers from copper.

"It will be appreciated that the general thrust of the microelectronic evolution is directed towards fabricating ever smaller, thinner and lighter and more powerful products having high reliability. The use of thick, cored interconnects, prevents ultra-thin products being attainable. To create ever higher densities of structures in the interconnect IC substrate or `interposer`, ever more layers of ever smaller connections are required. Indeed, sometimes it is desirable to stack components on top of each other.

"If plated, laminated structures are deposited on a copper or other appropriate sacrificial substrate, the substrate may be etched away leaving free standing, coreless laminar structures. Further layers may be deposited on the side previously adhered to the sacrificial substrate, thereby enabling a two sided build up, which minimizes warping and aids the attaining of planarity.

"One flexible technology for fabricating high density interconnects is to build up pattern or panel plated multilayer structures consisting of metal vias or features in a dielectric matrix. The metal may be copper and the dielectric may be a fiber reinforced polymer, typically a polymer with a high glass transition temperature (T.sub.g) is used, such as polyimide, for example. These interconnects may be cored or coreless, and may include cavities for stacking components. They may have odd or even numbers of layers. Enabling technology is described in previous patents issued to Amitec-Advanced Multilayer Interconnect Technologies Ltd.

"For example, U.S. Pat. No. 7,682,972 to Hurwitz et al. titled 'Advanced multilayer coreless support structures and method for their fabrication' describes a method of fabricating a free standing membrane including a via array in a dielectric, for use as a precursor in the construction of superior electronic support structures, includes the steps of fabricating a membrane of conductive vias in a dielectric surround on a sacrificial carrier, and detaching the membrane from the sacrificial carrier to form a free standing laminated array. An electronic substrate based on such a free standing membrane may be formed by thinning and planarizing the laminated array, followed by terminating the vias. This publication is incorporated herein by reference in its entirety.

"U.S. Pat. No. 7,669,320 to Hurwitz et al. titled 'Coreless cavity substrates for chip packaging and their fabrication' describes a method for fabricating an IC support for supporting a first IC die connected in series with a second IC die; the IC support comprising a stack of alternating layers of copper features and vias in insulating surround, the first IC die being bondable onto the IC support, and the second IC die being bondable within a cavity inside the IC support, wherein the cavity is formed by etching away a copper base and selectively etching away built up copper. This publication is incorporated herein by reference in its entirety.

"U.S. Pat. No. 7,635,641 to Hurwitz et al. titled 'integrated circuit support structures and their fabrication' describes a method of fabricating an electronic substrate comprising the steps of (A) selecting a first base layer; (B) depositing a first etchant resistant barrier layer onto the first base layer; (C) building up a first half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers; (D) applying a second base layer onto the first half stack; (E) applying a protective coating of photo-resist to the second base layer; (F) etching away the first base layer; (G) removing the protective coating of photo-resist ; (H) removing the first etchant resistant barrier layer; (I) building up a second half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers, wherein the second half stack has a substantially symmetrical lay up to the first half stack; (J) applying an insulating layer onto the second hall stack of alternating conductive layers and insulating layers, (K) removing the second base layer, and (L) terminating the substrate by exposing ends of vias on outer surfaces of the stack and applying terminations thereto. This publication is incorporated herein by reference in its entirety."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventor's summary information for this patent: "A first aspect of the invention is directed to providing a multilayer composite electronic structure comprising at least two feature layers extending in an X-Y plane and separated by a via layer comprising a dielectric material that is sandwiched between two adjacent feature layers, the via layer comprising via posts that couple adjacent feature layers in a Z direction perpendicular to the X-Y plane, wherein a first via post has different dimensions in the X-Y plane from a second via post in the via layer.

"Optionally, at least one of said via posts is substantially non-cylindrical.

"Optionally, the at least one via post comprises a seed layer covered by a metal layer deposited thereover by electroplating.

"Optionally, the seed layer comprises copper.

"Typically, the metal layer comprises copper.

"In some embodiments, the seed layer further comprises an adhesive metal layer first laid down to promote adhesion to the dielectric material.

"In some embodiments, the adhesive metal layer comprises at least one of the group comprising titanium, chromium, tantalum and tungsten.

"Optionally, the smallest dimension in the X-Y plane of a first via is at least 20% larger than the smallest dimension in the X-Y plane of a second via in the same plane.

"Optionally, a smallest dimension in the X-Y plane of a third via is at least 20% larger than the smallest dimension in the X-Y plane of the first via.

"Optionally, at least one via has a circular cross-section in the X-Y plane.

"Optionally, at least one via has a non-circular cross-section in the X-Y plane.

"In some embodiments, at least one via has a square cross-section in the X-Y plane.

"In some embodiments, at least one via is asymmetrical in the X-Y plane, having a linear shape.

"In some embodiments, at least one via at least one via is asymmetrical in the X-Y plane, extending in a first direction in the X-Y plane, at least three times the extension in a second direction in the X-Y plane that is perpendicular to the first direction.

"In some embodiments, at least one via has a diameter of less than 50 microns.

"In some embodiments, at least one via has a diameter of less than 40 microns.

"In some embodiments, at least one via has a diameter of 30 microns or less.

"In some embodiments, the thickness of the structure in the Z direction exceeds 50 microns.

"In some embodiments, a feature layer and the at least one via layer may be fabricated by a process comprising the steps of:

"(a) obtaining a substrate including an underlying via layer that is treated to expose the copper thereof; (b) covering the substrate with a seed layer; applying a first layer of photoresist over the seed layer; (d) exposing and developing the photoresist to form a negative pattern of features; (e) depositing metal into the negative pattern to fabricate the feature layer; (f) stripping away the first layer of photoresist; (g) applying a second layer of photoresist; (h) exposing and developing a negative pattern including at least two via posts of different dimensions in the negative pattern; (e) depositing a metal layer into the negative pattern; (f) stripping away the photoresist leaving the feature layer and the at least two via posts of different dimensions in the via layer upstanding; (k) removing the seed layer, (l) laminating a dielectric material over the at least two via posts in the via layer.

"Typically, at least one of the following limitations applies:

"(i) the seed layer comprises copper; (ii) the metal layer comprises copper; (iii) the dielectric material comprises a polymer, and (iv) the dielectric material further comprises ceramic or glass inclusions.

"Optionally, at least one of the following limitations applies: (i) the polymer comprises polyimide, epoxy, Bismaleimide, Triazine and blends thereof; (ii) the inclusions comprise glass fibers, and (iii) the inclusions comprise ceramic particle fillers.

"The process may comprise the further step: (m) planarizing to expose the metal.

"The method may comprise the further step: (n) depositing a metal seed layer over the ground surface.

"Optionally, the metal seed layer comprises copper.

"In some embodiments, the at least one via layer is fabricated by the steps of:

"(i) obtaining a substrate including an underlying feature layer where the copper thereof is exposed; (ii) covering the substrate with a seed layer; (iii) depositing a metal layer over the seed layer; (iv) applying a layer of photoresist over the metal layer; (v) exposing and developing a positive pattern of vias; (vi) etching away the metal layer exposed; (vii) stripping away the photoresist, leaving at least two vias of different dimensions in the via layer upstanding, (viii) removing the seed layer, and (xi) laminating a dielectric material over the at least two vias.

"Typically, at least one of the following limitations applies: (a) the seed layer comprises copper; (b) the metal layer comprises copper; the dielectric material comprises a polymer, and (d) the dielectric material further comprises ceramic or glass inclusions.

"Optionally, at least one of the following limitations applies: (e) the polymer comprises polyimide, epoxy, Bismaleimide, Triazine and blends thereof; (f) the inclusions comprise glass fibers, and (g) the inclusions comprise ceramic fillers.

"The method may comprise the further step: (x) planarizing and thinning to expose the metal.

"The method may comprise the further step: (xi) depositing a metal seed layer over the thinned surface.

"Optionally, the metal seed layer comprises copper.

"The term microns or .mu.m refers to micrometers, or 10.sup.-6 m."

For more information, see this patent: Hurwitz, Dror. Multilayer Electronic Structures with Vias Having Different Dimensions. U.S. Patent Number 8816218, filed May 29, 2012, and published online on August 26, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8816218.PN.&OS=PN/8816218RS=PN/8816218

Keywords for this news article include: Legal Issues, Technology, Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.

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Source: Journal of Technology


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