The patent's assignee for patent number 8818760 is
News editors obtained the following quote from the background information supplied by the inventors: "For years, processor designers were able to fully leverage Moore's Law, which states that the density of components integrated on a single chip grows exponentially over time. In conjunction with increasing chip density, chip clock rates have previously been following a trend of doubling approximately every 18 months. However, due to the increasing power requirements of processors, this clock frequency scaling is no longer possible. Instead, processor manufacturers have moved to designing multi-core processor systems, leveraging increasing chip density and possible spatial parallelism while clock rates remain relatively constant. It is predicted that the number of processors in multi-core systems will eventually scale to the 10 s and 100 s. This becomes a significant challenge for the Operating System (OS), which has to determine how to schedule tasks effectively on these complex systems. How will the OS determine how to schedule threads so as to minimize cache contention and which processor(s) meet each task's execution requirements on heterogeneous systems?
"Currently a number of hardware counters are included as part of a processor's architecture that enable limited profiling of applications at run time. However, these do not provide sufficient flexibility or information to effectively guide the OS in task assignment. While existing counters report the symptoms of a problem (i.e., how large the cache miss rate is), they do not provide insight into why the problem has occurred and how it could be fixed.
"Recent advances in integrated circuit technology have opened the door to very complex computation platforms. These platforms provide the high performance needed for both existing and many emerging applications. Many of these platforms contain multiple processors on a single chip. These modern multicore processors, also known as Multi-Processor Systems-on-Chip (MPSoC), contain multiple processing units sharing the caches and bus/point-to-point interconnects. This intimate sharing of resources among the cores leads to many opportunities for performance optimizations through co-operative sharing of resources, but also may cause performance degradation through shared resource contention. Since the introduction of multicore architectures into mainstream computing, much research effort has been dedicated to finding means for exploiting these opportunities and eliminating the problems. The challenge in these endeavours is that different workloads (programs running on the computer) have very different properties, meaning the resource management policy must also depend on the workload. To that end, researchers have strived for improved observability into performance on multicore processors.
"Existing observability tools, such as simple hardware performance counters, do not give enough information to address these issues, and so as a result, many proposals for more complex hardware counter architectures have emerged. These new architectures were a significant improvement over the existing state-of-the-art in that they allowed profound understanding of the properties of workloads and their interactions with multicore hardware. Unfortunately, their implementation in real processors required modifications to the processors underlying operation and architecture, and this proved to be a barrier for bringing these fruitful ideas to real devices. Many of the proposals for new observability enhancements remain research prototypes."
As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "It is an object of the present invention to provide a discrete configurable profiling core system that addresses some of the limitations of the prior art.
"According to one embodiment of the present invention, a computer system comprising at least one non-configurable hard processor (also well known in the art as a 'hard processor' or a 'processor' in contrast to a 'soft processor' or 'reconfigurable processor') with at least one non-configurable hard processor core (also well known in the art as a 'hard processor core' or a 'processor core' in contrast to a 'soft processor core' or 'reconfigurable processor core') is provided, where the computer system further comprises at least one discrete profiling core separate from the at least one processor, and wherein the at least one discrete profiling core comprises:
"at least one processor interface module operable to receive processing signals from the at least one non-configurable hard processor core; and
"at least one profiling module operable to analyze at least a portion of the processing signals to profile at least one processing performance measure; and wherein the at least one profiling core is operable to be configured during operation.
"According to another embodiment, a configurable profiling core is provided for use in a computer system comprising at least one non-configurable hard processor (also well known in the art as a 'hard processor' or a 'processor' in contrast to a 'soft processor' or 'reconfigurable processor') separate from the configurable profiling core and having at least one non-configurable hard processor core (also well known in the art as a 'hard processor core' or a 'processor core' in contrast to a 'soft processor core' or 'reconfigurable processor core'), wherein the configurable profiling core comprises:
"at least one processor interface module operable to receive processing signals from at least one non-configurable hard processor core; and
"at least one profiling module operable to analyze at least a portion of the processing signals to profile at least one processing performance measure; wherein the profiling core is operable to be configured during operation.
"According to another embodiment of the present invention, a modular dynamically re-configurable profiling core is provided which may be used to provide both operating systems and applications with detailed information about run time performance bottlenecks and may enable them to address these bottlenecks via scheduling or dynamic compilation. As a result, application software may be able to better leverage the intrinsic nature of the multi-core hardware platform, be it homogeneous or heterogeneous. In one embodiment, the profiling functionality may be desirably isolated on a discrete, separate and modular profiling core, which may be referred to as a configurable profiler (CP). In another embodiment, this modular configurable profiling core may facilitate inclusion of rich profiling functionality into new processors via modular reuse of the inventive CP. According to a further embodiment of the invention, the incorporation of the modular configurable profiling core may improve a customer's experience and productivity when used in conjunction with commercial multi-core processors.
"In one embodiment of the present invention, it is an object to provide designers with observability of tasks executing on heterogeneous multicore systems at run time to understand how to best leverage the processing resources of the system. In another embodiment, it is an object to provide operating system scheduling algorithms that leverage detailed run time statistics of applications to determine which processor(s) meet their execution requirements on heterogeneous multicore systems, and how to map applications to cores on systems with shared caches/memory so as to minimize cache/memory contention. In a further embodiment, it is an object for a performance profiling system incorporating a configurable profiling core to provide interpreted and/or guided processor performance profile information to designers comprising recommendations on how to optimize applications running on multicore processor systems."
For additional information on this patent, see: Shannon,
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