News Column

Patent Issued for Clock Integrated Circuit

September 9, 2014



By a News Reporter-Staff News Editor at Journal of Technology -- Macronix International Co., Ltd. (Hsinchu, TW) has been issued patent number 8819473, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventors are Chen, Chung-Kuang (Pan Chiao, TW); Hung, Chun-Hsiung (Hsinchu, TW); Chen, Han-Sung (Hsinchu, TW).

This patent was filed on November 1, 2013 and was published online on August 26, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "The present technology relates to an integrated circuit with a clock circuit, tolerant to variations such as temperature, ground noise, and power noise.

"The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Because these variations affect the final timing of the output clock signal, various approaches address the variations in order to generate a uniform output clock signal despite the variations.

"For example, U.S. Pat. No. 7,142,005 by Gaboury seeks to decouple power fluctuations from the clock signal, by adding buffer circuits with active loads, independent bias circuitry, and bias circuitry. These relatively complicated buffer circuits devote significantly more die area, and cost, to isolating such power fluctuations from the clock circuit.

"What is needed is an approach to address such variations with reduced complexity and cost."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "One aspect of the technology is an apparatus with a clock integrated circuit.

"The clock integrated circuit has a timing circuit with an output alternating between a first reference signal and a second reference signal at a rate determined by a time constant determining timing of a clock signal output of the clock integrated circuit. The second reference signal includes a varying noise signal, such as varying power noise.

"The clock integrated circuit also has clock power and reference circuitry, which has the varying noise signal. The clock power and reference circuitry generates the second reference signal with a first version of the varying noise signal. The clock power and reference circuitry also generates a level switching reference signal with a second version of the varying noise signal. The first version of the varying noise signal is synchronized with the second version of the varying noise signal, such that variations in the first version of the varying noise signal are synchronized with variations in the second version of the varying noise signal.

"The clock integrated circuit also has a level switching circuit comparing an output of the timing circuit with the level switching circuit reference signal. An output of the level switching circuit determines the clock signal output of the clock integrated circuit.

"In one embodiment, the variations in the first version of the varying noise signal have different magnitudes from the variations in the second version of the varying noise signal.

"In one embodiment, the clock power and reference circuitry has a first output for the second reference signal, and a second output for the level switching reference signal, and the varying noise signal is synchronized across the first output and the second output via a resistance coupled between the first output and the second output. In one embodiment, the varying noise signal is synchronized across the first output and the second output via a capacitance coupled between the first output and the second output. In one embodiment, one of the first output and the second output is floating for this capacitive coupling.

"One embodiment further includes switches decoupling the level switching circuit during power on.

"In one embodiment, the first reference signal is a first reference voltage, the second reference signal is a second reference voltage, and the timing circuit alternates between charging from the first reference voltage to the second reference voltage and discharging from the second reference voltage to the first reference voltage.

"In one embodiment, the time constant characterizes an exponential signal.

"In one embodiment, the clock integrated circuit further includes a latch circuit generating the clock signal output of the clock integrated circuit, responsive to the output of the level switching circuit.

"Some embodiments include a level switching reference circuit generating the level switching reference signal. The level switching reference circuit includes an output generating the level switching reference signal. In various embodiments the level switching reference circuit includes a PTAT current generator or CTAT current generator, that generates current flowing by the output. In various embodiments the level switching reference circuit includes a resistance adjacent to the output or a parallel resistance and capacitance adjacent to the output.

"One aspect of the technology is a clocking method. Some embodiments include the steps of:

"determining timing of a clock integrated circuit by alternating a timing circuit output between a first reference signal and a second reference signal at a rate determined by a time constant determining the timing of the clock integrated circuit;

"generating the second reference signal with a first version of a varying noise signal and a level switching reference signal with a second version of the varying noise signal, the first version of the varying noise signal synchronized with the second version of the varying noise signal, such that variations in the first version of the varying noise signal are synchronized with variations in the second version of the varying noise signal; and

"comparing the timing circuit output with the level switching reference signal, to determine a clock signal output of the clock integrated circuit.

"In some embodiments, the varying noise signal is a varying power noise.

"In some embodiments, the variations in the first version of the varying noise signal have different magnitudes from the variations in the second version of the varying noise signal.

"In some embodiments, said generating includes:

"synchronizing the first version and the second version of the varying noise signal by coupling the second reference signal and the level switching reference signal with a resistance.

"In some embodiments, said generating includes:

"synchronizing the first version and the second version of the varying noise signal by coupling the second reference signal and the level switching reference signal with a capacitance.

"In some embodiments, said generating includes:

"synchronizing the first version and the second version of the varying noise signal by floating one of the second reference signal and the level switching reference signal, and coupling the second reference signal and the level switching reference signal with a capacitance.

"Some embodiments further include:

"decoupling the synchronized versions of the varying noise signal during power on, such that said determining and said comparing do not rely on the synchronized versions of the varying noise signal during power on.

"In some embodiments, the first reference signal is a first reference voltage, the second reference signal is a second reference voltage, and the timing circuit alternates between charging from the first reference voltage to the second reference voltage and discharging from the second reference voltage to the first reference voltage.

"In some embodiments, the time constant characterizes an exponential signal.

"Some embodiments further include:

"after said comparing, generating the clock signal output of the clock integrated circuit with a latch circuit.

"One aspect of the technology is a method of manufacturing an apparatus, comprising:

"providing a clock integrated circuit, comprising:

"providing a timing circuit having an output alternating between a first reference signal and a second reference signal at a rate determined by a time constant determining timing of a clock signal output of the clock integrated circuit, the second reference signal including a varying noise signal;

"providing clock power and reference circuitry having the varying noise signal, the clock power and reference circuitry generating the second reference signal with a first version of the varying noise signal, the clock power and reference circuitry generating a level switching reference signal with a second version of the varying noise signal, the first version of the varying noise signal synchronized with the second version of the varying noise signal, such that variations in the first version of the varying noise signal are synchronized with variations in the second version of the varying noise signal; and

"providing a level switching circuit comparing an output of the timing circuit with the level switching circuit reference signal, an output of the level switching circuit determining the clock signal output of the clock integrated circuit."

For the URL and additional information on this patent, see: Chen, Chung-Kuang; Hung, Chun-Hsiung; Chen, Han-Sung. Clock Integrated Circuit. U.S. Patent Number 8819473, filed November 1, 2013, and published online on August 26, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8819473.PN.&OS=PN/8819473RS=PN/8819473

Keywords for this news article include: Macronix International Co., Macronix International Co. Ltd., Technology.

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Source: Journal of Technology


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