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Patent Application Titled "Semiconductor Device Having Storage Electrode and Manufacturing Method Thereof" Published Online

September 12, 2014



By a News Reporter-Staff News Editor at Health & Medicine Week -- According to news reporting originating from Washington, D.C., by NewsRx journalists, a patent application by the inventor MIYAJIMA, Takashi (Tokyo, JP), filed on April 29, 2014, was made available online on August 28, 2014 (see also Elpida Memory, Inc.).

The assignee for this patent application is Elpida Memory, Inc.

Reporters obtained the following quote from the background information supplied by the inventors: "The present invention relates to a semiconductor device having a storage electrode and a manufacturing method thereof.

"Priority is claimed on Japanese Patent Application No. 2008-193389, filed Jul. 28, 2008, the content of which is incorporated herein by reference.

"Accompanying developments in miniaturization and high-integration of DRAM, the size of capacitor elements that form a memory cell has also been reduced. Consequently, it is becoming more difficult to ensure a sufficient amount of accumulated charge. In order to improve capacitor capacity, there is a need to expand the surface area of the capacitor elements. Therefore, as a stack type capacitor element, there has been developed a capacitor having a cylindrical (cylinder-shaped) lower electrode.

"As capacitor elements become miniaturized, the diameter of the cylinder opening of the cylindrical lower electrode and its surface area is reduced. As a result, the capacitor capacity becomes smaller. Consequently, in order to ensure capacitor capacity, in simple terms, the height of the lower electrode needs to be heightened to thereby increase the surface area.

"However, we have now discovered that there has been a problem in that if an attempt is made so that the height of the lower electrode is ensured and a cylinder shape is formed in the deep section of the lower electrode, defects will occur in the dry etching because the aspect ratio of the lower electrode is high. That is to say, etching gas is unlikely to penetrate into the deep section of the lower electrode, and the control of dry etching becomes more difficult. Consequently, there is a possibility that the cylinder opening becomes defective and the shape of the lower electrode becomes unstable. Furthermore, there is a possibility that if the shape of the lower electrode becomes unstable, the lower electrode may collapse, causing a short failure between adjacent electrodes.

"Japanese Unexamined Patent Application, First Publication No. 2004-311918 (hereinafter, referred to as Patent Document 1) discloses a semiconductor device in which there is provided a two-stage structure in a lower electrode of a capacitor to thereby enable a reduction in dry etching defects. That is to say, Patent Document 1 discloses a semiconductor device in which, as shown in FIG. 15 of Patent Document 1, in an interlayer insulating film 102 with an etching stopper film 10 formed thereon, there is formed a storage node contact plug 104. This semiconductor device has a capacitor lower electrode 106 having a two-stage structure of a pad-shaped storage node (first storage electrode) 40 formed so as to connect to the storage node contact plug 104, and a cup-shaped storage node (second storage electrode) 70 formed thereon. As a result, the capacitor lower electrode 106 is formed high and the capacitor capacity is ensured, and only the second storage electrode 70 is formed in a cup shape. Therefore, it is alleged to be possible to reduce defects in dry etching, that is, defects in the opening, or defects in the shape of the capacitor lower electrode 106.

"However, we have recognized that even in the case of using the two-stage structured capacitor lower electrode 106 shown in FIG. 15 of Patent Document 1, with further miniaturization of the device, the influence of superposition displacement in lithography becomes significant. Therefore, there is a possibility that again defects such as collapse of the capacitor and deterioration in the capacitor characteristic may occur. A problem in the conventional art is more specifically described with reference to FIG. 21. FIG. 21 is illustrated by adding to FIG. 15 of Patent Document 1 which discloses the conventional art a phenomenon which causes the problem discovered by the present inventor.

"As shown in FIG. 21, when forming the two-stage structured capacitor lower electrode 106, the positions of the pad-shaped storage node (first storage electrode) 40 and the cup-shaped storage node (second storage electrode) 70 may be displaced from each other in some cases due to superposition displacement in lithography. In this case, there is a problem in that the contact area between the first storage electrode 40 and the second storage electrode 70 is reduced. As a result there is a possibility that the mechanical strength of the capacitor lower electrode 106 is reduced and the second storage electrode 70 consequently collapses, causing short-circuit between the adjacent capacitor lower electrodes. Moreover, there is a possibility that even if a short-circuit does not occur, since stress is applied to the capacitive insulating film that coats the capacitor lower electrode 106, leakage current may increase."

In addition to obtaining background information on this patent application, NewsRx editors also obtained the inventor's summary information for this patent application: "In one embodiment, there is provided a semiconductor device that includes: a first storage electrode; a second storage electrode that is arranged above the first storage electrode; a first landing pad that is arranged between a top surface of the first storage electrode and a bottom surface of the second storage electrode, the first landing pad connecting the first storage electrode and the second storage electrode, the first landing pad having a first landing surface, the first landing surface being larger than the bottom surface of the second storage electrode, and the second storage electrode being placed on the first landing surface.

"In another embodiment, there is provided a method for manufacturing a semiconductor device that includes: laminating a first insulating film over a capacitor contact plug; forming a first storage electrode that is embedded in the first insulating film; forming a recess over the first storage electrode in the first insulating film, at the top level of the first insulating film the recess being larger in dimension than the top surface of the first storage electrode; forming a first landing pad in the recess, the first landing pad having a first landing surface; forming a second insulating film that covers the first insulating film and the first landing pad; forming a second storage electrode that is embedded in the second insulating film so that the second storage electrode has a bottom surface that contacts the first landing surface, the bottom surface of the second storage electrode being smaller than the first landing surface.

BRIEF DESCRIPTION OF THE DRAWINGS

"The above features and advantages of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which:

"FIG. 1 is a schematic sectional view showing a semiconductor device according to a first embodiment of the present invention;

"FIG. 2A is a plan view showing a process involved in a method for manufacturing the semiconductor device of the first embodiment;

"FIG. 2B is a sectional view taken along the line A-A' shown in FIG. 2A;

"FIG. 3A is a plan view showing a process involved in the method for manufacturing the semiconductor device of the first embodiment;

"FIG. 3B is a sectional view taken along the line A-AI shown in FIG. 3A;

"FIG. 4 is a process sectional view showing a process involved in the method for manufacturing the semiconductor device of the first embodiment;

"FIG. 5 is a process sectional view showing a process involved in the method for manufacturing the semiconductor device of the first embodiment;

"FIG. 6 is a process sectional view a process involved in showing the method for manufacturing the semiconductor device of the first embodiment;

"FIG. 7 is a process sectional view showing a process involved in the method for manufacturing the semiconductor device of the first embodiment;

"FIG. 8 is a process sectional view showing a process involved in the method for manufacturing the semiconductor device of the first embodiment;

"FIG. 9 is a process sectional view showing a process involved in the method for manufacturing the semiconductor device of the first embodiment;

"FIG. 10 is a schematic sectional view showing a semiconductor device according to a second embodiment of the present invention;

"FIG. 11 is a process sectional view showing a process involved in a method for manufacturing the semiconductor device of the second embodiment;

"FIG. 12 is a process sectional view showing a process involved in the method for manufacturing the semiconductor device of the second embodiment;

"FIG. 13 is a process sectional view showing a process involved in the method for manufacturing the semiconductor device of the second embodiment;

"FIG. 14 is a schematic sectional view showing a semiconductor device according to a third embodiment of the present invention;

"FIG. 15 is a process sectional view showing a process involved in a method for manufacturing the semiconductor device of the third embodiment;

"FIG. 16 is a process sectional view showing a process involved in the method for manufacturing the semiconductor device of the third embodiment;

"FIG. 17 is a process sectional view showing a process involved in the method for manufacturing the semiconductor device of the third embodiment;

"FIG. 18 is a process sectional view showing a process involved in the method for manufacturing the semiconductor device of the third embodiment;

"FIG. 19 is a schematic sectional view showing a modified example of the semiconductor device according to the third embodiment of the present invention;

"FIG. 20 is a graph showing leakage current characteristics of a semiconductor device of a working example of the present invention and of a semiconductor device of a comparative example; and

"FIG. 21 is a schematic sectional view for describing problems of a semiconductor device of a conventional art having a two-stage capacitor."

For more information, see this patent application: MIYAJIMA, Takashi. Semiconductor Device Having Storage Electrode and Manufacturing Method Thereof. Filed April 29, 2014 and posted August 28, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=5736&p=115&f=G&l=50&d=PG01&S1=20140821.PD.&OS=PD/20140821&RS=PD/20140821

Keywords for this news article include: Electronics, Elpida Memory, Elpida Memory Inc., Microtechnology, Semiconductor.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


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Source: Health & Medicine Week


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