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Findings from KTH Royal Institute of Technology Provides New Data on Microprocessors and Microsystems (A survey of memory architecture for 3D chip...

September 10, 2014

Findings from KTH Royal Institute of Technology Provides New Data on Microprocessors and Microsystems (A survey of memory architecture for 3D chip multi-processors)

By a News Reporter-Staff News Editor at Electronics Newsweekly -- Investigators publish new report on Microprocessors and Microsystems. According to news originating from Stockholm, Sweden, by VerticalNews correspondents, research stated, "3D chip multi-processors (3D CMPs) combine the advantages of 3D integration and the parallelism of CMPs, which are emerging as active research topics in VLSI and multi-core computer architecture communities. One significant potentiality of 3D CMPs is to exploit the diversity of integration processes and high volume of vertical TSV bandwidth to mitigate the well-known 'Memory Wall' problem."

Our news journalists obtained a quote from the research from the KTH Royal Institute of Technology, "Meanwhile, the 3D integration techniques are under the severe thermal, manufacture yield and cost constraints. Research on 3D stacking memory hierarchy explores the high performance and power/thermal efficient memory architectures for 3D CMPs. The micro-architectures of memories can be designed in the 3D integrated circuit context and integrated into 3D CMPs. This paper surveys the design of memory architectures for 3D CMPs. We summarize current research into two categories: stacking cache-only architectures and stacking main memory architectures for 3D CMPs."

According to the news editors, the research concluded: "The representative works are reviewed and the remaining opportunities and challenges are discussed to guide the future research in this emerging area."

For more information on this research see: A survey of memory architecture for 3D chip multi-processors. Microprocessors and Microsystems, 2014;38(5):415-430. Microprocessors and Microsystems can be contacted at: Elsevier Science Bv, PO Box 211, 1000 Ae Amsterdam, Netherlands. (Elsevier -; Microprocessors and Microsystems -

The news correspondents report that additional information may be obtained from Y. Zhang, KTH Royal Inst Technol, Dept. of Elect Comp & Software Syst, Sch Informat & Commun Technol, Stockholm, Sweden. Additional authors for this research include L. Li, Z.H. Lu, A. Jantsch, M.L. Gao, H.B. Pan and F. Han.

Keywords for this news article include: Stockholm, Sweden, Europe, Microprocessors and Microsystems

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Source: Electronics Newsweekly

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