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"Dynamic Random Access Memory with Fully Independent Partial Array Refresh Function" in Patent Application Approval Process

September 10, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent application by the inventors KIM, Jin-Ki (Ottawa, CA); OH, HakJune (Ottawa, CA), filed on April 30, 2014, was made available online on August 28, 2014, according to news reporting originating from Washington, D.C., by VerticalNews correspondents.

This patent application is assigned to Conversant Intellectual Property Management Inc.

The following quote was obtained by the news editors from the background information supplied by the inventors: "In dynamic random access memory (DRAM) integrated circuit devices, a DRAM cell array is typically arranged in rows and columns such that a particular DRAM cell is addressed by specifying its row and column within the array. A wordline connects a row of cells to a set of bitline sense amplifiers that detect the data in the cells. In a read operation, a subset of the data in the bitline sense amplifiers is then chosen, or 'column-selected' for output. DRAM cells are 'dynamic' in the sense that the stored data, typically in the form of charged and discharged storage capacitors, will dissipate after a relatively short period of time. Thus, in order to retain the information, the contents of the DRAM cells must be refreshed. The charged or discharged state of the storage capacitor must be reapplied to an individual memory cell in a repetitive manner. The maximum amount of time allowable between refreshing operations is determined by the charge storage capabilities of the storage capacitors that make up the DRAM cell array. DRAM manufacturers typically specify a refresh time for which it guarantees data retention in the DRAM cells.

"A refresh operation is similar to a read operation, but no data is output. The sensing of the data in the cells by the bitline sense amplifiers is followed by a restoring operation that results in the data being rewritten to the cells. The data is, thus, 'refreshed'. The refresh operation is performed by enabling a wordline according to a row address, and enabling a bitline sense amplifier. In addition, the refresh operation may be carried out by operating the bitline sense amplifier without receiving an external refresh address. In this case, a refresh address counter, which is integrated in a DRAM device chip, generates a row address subsequent to receiving an external refresh command. It is well known that DRAM cells are refreshed by self-refresh function to retain stored data. The self-refresh function is one of performing refresh operations automatically within the DRAM when in a 'standby' mode to retain the data written in its memory cells.

"In low power DRAM devices for mobile applications, power consumption during a standby or sleep mode is critical. A major portion of power consumption during the standby or sleep mode is for refresh operation to retain data. Hence, the key for power reduction during the standby or sleep mode is to reduce the refresh frequency. In low power DRAM devices, one of the available power reduction features is a partial refresh that restricts refresh and self-refresh operation during the standby or sleep mode to a portion of the total memory array. This feature enables the device to reduce refresh current by refreshing only that part of the memory array required by a host system. That technique is a 'partial array refresh' that supports array selections of 1/4 array, 1/2 array or 3/4 array with fixed array location. For example, a partial array self-refresh power-saving function with a low power extended mode register is known (see, for example, Micron.RTM. 256 Mb:x32, MOBILE SDRAM, data sheet).

"In known partial array self-refresh scheme, a fixed and pre-determined partial array selection is performed as per mode register settings. It does not, thus, perform flexible combinations of array selection for power saving. In DRAM devices which are partitioned as 'banks', 'subblocks' or 'sub-arrays', the bank, subblock or sub-array addresses are key performance factors to achieve faster accesses to partial array memories. It is a simple solution, without DRAM performance degradation, to limit partial array self-refresh feature in low power DRAM devices. Therefore, the fixed and pre-determined scheme is a good compromise between the power saving and the DRAM performance.

"A simplified conventional DRAM device is shown in FIG. 1. Referring to FIG. 1 that shows an example DRAM device, a memory controller (not shown) provides it with commands and addresses for DRAM operation. The DRAM device has a full memory block consisting of four banks 112-0, 112-1, 112-2 and 112-3. An external command controller 121, which is synchronized with clocks, includes a command decoder that interprets the commands and generates a refresh request signal 123 indicating whether the memory blocks are to be refreshed or not. The commands include EMRS (extended mode register set) commands. When the EMRS commands are fed to the external command controller 121, an EMRS signal 125 is provided by the command decoder thereof.

"An extended mode register 131 writes information carried on selection addresses 'A[0:2]' therein in accordance with mode register set commands BA[0:1]. The selection addresses 'A[0:2]' give instructions for the partial array self-refresh (PASR) configuration. Once the PASR configuration information is written into the extended mode register 131, it provides a PASR signal 133, the bits of which indicate whether 'full array' should be refreshed or partial array should be refreshed in the self-refresh mode. In response to the refresh request signal 123 and the PASR signal 133, an internal bank address counter 135 generates an internal bank address signal 137 containing internal bank addresses that are fed to a multiplexer 141.

"Also, the mode register set commands BA[0:1] are latched by an external bank address latch 143. In accordance with the latched addresses, the external bank address latch 143 provides an external bank address signal 145 containing external bank addresses to the multiplexer 141. The multiplexer 141 selects the internal bank addresses or the external bank addresses in response to the refresh request signal 123.

"In response to '1' or '0' of the refresh request signal 123, the multiplexer 141 selects the internal bank addresses of the internal bank address signal 137 or the external bank addresses of the external bank address signal 145. The selected addresses are fed to a bank address decoder 151 which in turn provides a decoded address signal 153 to the full memory block consisting of four banks 112-0, 112-1, 112-2 and 112-3. The decoded address signal 153 contains four bank select signals 154-0, 154-1, 154-2 and 154-3. Therefore, the bank address decoder 151 enables one of the four bank select signals 154-0, 154-1, 154-2 and 154-3.

"In accordance with the mode register set commands BA[0:1] and the selection addresses 'A[0:2]', the banks are designated as shown in following Table 1:

"TABLE-US-00001 TABLE 1 A[2] A[1] A[0] Banks to be Self-Refreshed 0 0 0 Four Banks 0 0 1 Two Banks (e.g., Bank [0] and [1) 0 1 0 One Bank (e.g., Bank [0])

"In the DRAM device shown in FIG. 1, the PASR supports only the array selections of 1/4 array (i.e., one bank), 1/2 array (i.e., two banks) or 3/4 array (i.e., three banks) with fixed array location. The DRAM device has ability to save power consumption in the self-refresh mode, however it lacks of controllability of selecting which memory bank will be retained in the self-refresh mode. Such a low power DRAM design with the EMRS function allows a full memory array, a half memory array or a 1/4 memory array to be selected. When a 1/4 memory array is selected for self-refresh mode, for example, the DRAM device enables least significant banks for the selection of a 1/4 memory. It may not, thus, be possible to select the other memory banks for specific data retention. It may also not be possible to select another combination of banks, for example bank [0] and bank [3], for the self-refresh mode."

In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventors' summary information for this patent application: "It is an object of the present invention to provide an improved dynamic random access memory (DRAM) device with an independent partial array refresh function.

"In accordance with one aspect, there is provided a dynamic random access memory (DRAM) device including a memory having M memory subblocks, M being an integer greater than one. Each subblock has a plurality of wordlines. Each wordline is connected to a plurality of data store cells. The cells are refreshed by refresh operation. Also, the DRAM device includes a refresh circuit for controlling in a refresh mode the refreshing of the memory subblocks in accordance with M subblock refresh data independently set.

"Advantageously, the refresh circuit includes a configuration circuit for configuring the M subblock refresh data in response to input data. The M subblock refresh data is independently set by the input data. For example, the configuration circuit includes a latch circuit for holding the input data. The M subblock refresh data is produced in accordance with the held input data. The latch circuit may include M latching circuits for latching the M subblock refresh data. Each of the M latching circuit latches the respective one of the M subblock refresh data independently.

"In accordance with another aspect, there is provided a method for refreshing a dynamic random access memory device including M memory subblocks, M being an integer greater than one, each subblock having a plurality of wordlines, each wordline being connected to a plurality of data store cells, the cells being refreshed in a refresh mode. The method including controlling in a refresh mode the refreshing of the memory subblocks in accordance with M subblock refresh data independently set.

"For example, the step of controlling includes the step of configuring the M subblock refresh data in response to input data, the M subblock refresh data being independently set by the input data. The step of configuring includes the step of holding the input data, the M subblock refresh data being produced in accordance with the held input data.

"Advantageously, the method further includes the step of providing an address signal for selecting the subblock.

"In accordance with a further aspect, there is provided a refresh controller for use in a dynamic random access memory device selectively operated in a refresh mode and a non self-refresh mode, the DRAM device including M memory subblocks, M being an integer greater that one. Each subblock has a plurality of wordlines. Each wordline is connected to a plurality of data store cells. The cells are refreshed in a refresh mode. The refresh controller includes a refresh circuit for controlling in refresh mode the refreshing of the memory subblocks in accordance with M subblock refresh data independently set.

"Advantageously, the refresh controller further includes a configuration circuit for configuring the M subblock refresh data in response to input data, the M subblock refresh data being independently set by the input data.

"For example, the configuration circuit includes a latch circuit for holding the input data, the M subblock refresh data being produced in accordance with the held input data.

"In accordance with embodiments of the present invention, there is provided a DRAM device and a method for refreshing memory cells fully independent partial array refresh and self-refresh based on minimum compliable array size. Any kind of array combination can be selected and refreshed by input data selection. In the embodiments, unlimited controllability of array selection is achieved for refresh and self-refresh. Configurable partial array registration is performed by data input. The embodiments of the present invention achieve advantages; flexibility of selection of memory array blocks; unlimited combination of arrays for refresh and self-refresh; user selectable arrays for data retention provides effective memory control programming especially for low power mobile application.

"Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.

BRIEF DESCRIPTION OF THE DRAWINGS

"Embodiments of the present invention will now be described, by way of example only, with reference to the attached Figures, wherein:

"FIG. 1 is a schematic diagram illustrating a conventional address controller found in a dynamic random access memory (DRAM) device with a partial array self-refresh function;

"FIG. 2 is a schematic diagram illustrating a DRAM device according to one embodiment of the present invention;

"FIG. 3 is a schematic diagram illustrating a DRAM device according to an embodiment of the present invention;

"FIG. 4 is a schematic diagram illustrating a detailed circuit of a partial array self-refresh (PASR) configuration register shown in FIG. 3;

"FIG. 5 is a schematic diagram illustrating a detailed circuit of an external address decoder shown in FIG. 3;

"FIG. 6 is a schematic diagram illustrating a detailed circuit of an internal address decoder shown in FIG. 3;

"FIG. 7 is a schematic diagram illustrating a detailed circuit of subblock selectors and a memory shown in FIG. 3;

"FIG. 8 is a schematic diagram illustrating an example of the addressing of the subblocks of the memory shown in FIG. 3;

"FIG. 9 is a flowchart illustrating the operation of the DRAM device shown in FIG. 3;

"FIG. 10 is a flowchart illustrating the self-refresh operation of the DRAM device shown in FIG. 3;

"FIG. 11 is a flowchart illustrating the normal operation of the DRAM device shown in FIG. 3;

"FIG. 12 is a schematic diagram illustrating a DRAM device according to another embodiment of the present invention;

"FIG. 13 is a schematic diagram illustrating a detailed circuit of a PASR configuration register shown in FIG. 12;

"FIG. 14 is a schematic diagram illustrating a detailed circuit of a selector and an address decoder shown in FIG. 12;

"FIG. 15 is a schematic diagram illustrating a detailed circuit of a subblock selectors and a memory shown in FIG. 12; and

"FIG. 16 is a flowchart illustrating the operation of the DRAM device shown in FIG. 12."

URL and more information on this patent application, see: KIM, Jin-Ki; OH, HakJune. Dynamic Random Access Memory with Fully Independent Partial Array Refresh Function. Filed April 30, 2014 and posted August 28, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4370&p=88&f=G&l=50&d=PG01&S1=20140821.PD.&OS=PD/20140821&RS=PD/20140821

Keywords for this news article include: Electronics, Random Access Memory.

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Source: Electronics Newsweekly


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