Patent number 8792286 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "Exemplary embodiments relate generally to an integrated circuit, and more particularly to a semiconductor memory device and an operating method thereof.
"A nonvolatile memory device retains data stored therein even in absence of power supply. The nonvolatile memory device includes a flash memory device. The flash memory device may be divided into a NOR flash memory device and a NAND flash memory device according to the structure of a memory cell array. The gate of the flash memory cell includes, for example, a tunnel insulating layer, a floating gate, a dielectric layer, and a control gate.
"In the case of the NAND flash memory device, a program operation and an erase operation are performed through F-N tunneling. In addition, the floating gate is accumulated with electrons by the program operation, and the electrons accumulated in the floating gate are discharged to a substrate by the erase operation. Furthermore, when a read operation is performed, the threshold voltage of a memory cell, shifted depending on the amount of electrons accumulated in the floating gate, is detected, and data is read on the basis of the detected threshold voltage.
"In the operation of detecting the threshold voltage of the memory cell, a random telegraph noise (RTN) phenomenon may occur and thus the threshold voltage of the memory cell may vary according to whether electrons are trapped in or released from the floating gate of the memory cell. In other words, detected threshold voltage of a memory cell may vary even though data stored in the memory cell has not changed owing to the RTN phenomenon. The RTN phenomenon makes it difficult to narrow the width of a distribution of the threshold voltages of memory cells because the threshold voltages of the memory cells verified in a programming process are shifted."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventor's summary information for this patent: "Exemplary embodiments relate to a semiconductor memory device and an operating method thereof which are capable of narrowing a distribution of the threshold voltages of memory cells by repeatedly reading data from the same memory cell by a set number and determining the mean value of read data as data of the memory cell.
"A semiconductor memory device according to an aspect of the present disclosure includes a page buffer configured to store data read from a memory cell, a counter circuit configured to count the number of first data or second data in the read data for every read operation while the read operations are repeated a set number of times, and a control logic configured to determine the number of read operations and determine the read data of the memory cell based on the counted number.
"A data read method of a semiconductor memory device according to an aspect of the present disclosure includes repeating a read operation on a first memory cell a set number of times by using a first read voltage in response to a read command, counting the number of first data or second data in data read while the read operations are repeated, and determining the data, stored in the memory cell, based on the counted number of first or second data.
"A data read method of a semiconductor memory device according to another aspect of the present disclosure includes repeating a read operation a set number of times using a first read voltage in order to read most significant bit (MSB) data stored in a memory cell, counting the number of first data or second data in read data for every read operation, and determining first read data based on the counted number of first data or second data."
URL and more information on this patent, see: Joo,
Keywords for this news article include: Electronics,
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OCTOBER 31, 2014
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