News Column

Patent Issued for Computational Lithography with Feature Upsizing

August 13, 2014

By a News Reporter-Staff News Editor at Journal of Engineering -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventors Parikh, Ashesh (Frisco, TX); Ho, Chi-Chien (Plano, TX); Smelko, Thomas John (Richardson, TX), filed on March 22, 2013, was published online on July 29, 2014.

The patent's assignee for patent number 8793626 is Texas Instruments Incorporated (Dallas, TX).

News editors obtained the following quote from the background information supplied by the inventors: "Optical proximity correction (OPC) is a photolithography enhancement technique commonly used to compensate for image errors due to diffraction effects or process effects. OPC is needed mainly in the making of semiconductor devices and is due to the limitations of electromagnetic radiation to maintain the edge placement integrity of the original design, after processing, into the etched feature on the wafer. These projected images appear with irregularities such as line widths that are narrower or wider than designed, and are amenable to OPC compensation by changing the pattern on the photomask (or reticle) used for the imaging.

"OPC corrects these errors by moving edges or adding extra polygons to the pattern written on the photomask. This may be driven by pre-computed look-up tables based on width and spacing between the features (known as rule-based OPC), or by using compact models to dynamically simulate the final pattern and thereby drive the movement of edges, typically broken into sections, to find the best solution. The objective is to reproduce, as well as possible, the original IC layout drawn by the IC designer into features etched on the die of the wafer.

"The workhorse to enable sub-wavelength lithography is referred to as computational lithography (CL). CL makes use of numerical simulations to improve the performance (resolution and contrast) provided by cutting-edge reticles. CL combines techniques including Resolution Enhancement Technology (RET), OPC, and some non-optical portions. Beyond the models used for RET and OPC, CL can include the signature of the scanner to help improve the accuracy of the OPC model, polarization characteristics of the lens pupil, a Jones matrix of the stepper lens, optical parameters of the resist stack, and diffusion through the resist.

"For example, in the sub-wavelength lithography era, off-axis illumination such as Annular and Quadropole has been used to print high density features. While the process margin for certain features has been improved, other features notably line-ends and corners, suffer from high sensitivity to focus variation, and thus have a low depth of focus (DOF) which is also known as the depth of field. DOF is the range of distances in object space for which object points are imaged with acceptable sharpness with a fixed position of the image plane. OPC corrects for size only, as it only adjusts the reticle/mask to bring the feature to the designed size at the best focus and dose conditions."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "Disclosed embodiments recognize integrated circuits (ICs) manufactured using sub-wavelength lithography and conventional computational lithography (CL) including optical proximity correction (OPC) are subject to high parametric variability due to lower process margins that can cause yield loss including shifted parameters (e.g., capacitance, resistance, drive current), as well as open and short circuits. Differential sensitivity of focus variation (reflected in Bossung curves) for different feature types is also recognized by disclosed embodiments, with smaller focus sensitivity of CDs for dense feature types and more focus sensitivity for CDs of isolated feature types, where high-frequency features such as line ends are also found to be generally more focus sensitive. CL models with feature upsizing is described herein that includes identifying if any of the feature types are 'marginal' feature types, and if there are marginal feature(s) present, upsizing at least the marginal feature types which enables re-centering the parametric data associated with the marginal feature types. The features can be spaces or lines, where in the case of spaces for the features, disclosed upsizing results in the thinning of the lines.

"Marginal feature types can be defined as feature types which have Bossung curves that include CD data beyond a predetermined variance (or error) relative to a nominal CD value. Disclosed feature upsizing is operable to reduce parametric the failures at the lower end of the parametric specification, such as resistance, capacitance, or drive current.

"As used herein, the term 'feature type' refers to the ratio of line width to space width in a given pattern portion (from a grating having repetitive lines and/or spaces on a reticle) of a lithography level, with each different feature type having a different ratio of line width to space width. Different feature types thus provide different pattern densities with resulting different optical interference effects. Different feature types may provide different pitches, defined in the art as the period of the grating. The artisan with ordinary skill in the art will appreciate that the term 'mask' and 'reticle', should be considered to be equivalent.

"Disclosed embodiments include methods of CL including providing data from a plurality of different feature types which include different ratios of line width to space width to provide through-data CD data curves (Bossing curves having CD data at a range of different focus values). Marginal feature type(s) are determined to see if present from the plurality of feature types based an image tool capability, and a predetermined process specification affected by at least one of the plurality of feature types. Image tool capability generally includes dipole center sigma, focus blur (focus blur nominally refers to deviation from ideal image due to finite laser band-width, vertical mechanical vibration and/or reticle wafer stage tilt), source shape, numerical aperture (NA), and lens aberration. The predetermined process specification can comprise an electrical parameter (e.g., drive current for a MOS transistor), a CD distribution (e.g., CD size range or .sigma.), or a depth of field (DOF).

"If at least one marginal feature type is identified, at least the marginal feature type(s) are upsized in the design. In another embodiment, all of the feature types in the design are upsized. More sensitive feature types reflected in their Bossung curves are upsized more than less sensitive feature types by upsizing by a fixed amount relative to their .sigma. reflected in their respective Bossung curves. A CL model is compiled including the upsizing at least the marginal feature types, such as running the CL model in one particular embodiment at 1.5.sigma. for the marginal features types' CD vs. focus distribution reflected in their Bossung curves. The method can further comprise performing CL using the CL model to design a reticle for at least one level for fabricating an integrated circuit (IC)."

For additional information on this patent, see: Parikh, Ashesh; Ho, Chi-Chien; Smelko, Thomas John. Computational Lithography with Feature Upsizing. U.S. Patent Number 8793626, filed March 22, 2013, and published online on July 29, 2014. Patent URL:

Keywords for this news article include: Texas Instruments Incorporated.

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Source: Journal of Engineering

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