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Patent Issued for Power Semiconductor Device Including a Double Metal Contact

August 13, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent by the inventors Montgomery, Robert (South Glamorgan, GB); Burke, Hugo (Cardiff, GB); Parsonage, Philip (Vale of Glamorgan, GB); Johns, Susan (Splott Cardiff, GB); Jones, David Paul (Cardiff, GB), filed on February 25, 2008, was published online on July 29, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8791525 is assigned to International Rectifier Corporation (El Segundo, CA).

The following quote was obtained by the news editors from the background information supplied by the inventors: "Conventional power MOSFETs use a thick (4 to 10 .mu.m) top layer of metalization for connection to the source regions thereof due to the large currents that the metal has to conduct during the operation of the device. Because of the thickness of the top metal, wet etching is used to pattern the same during fabrication. The use of wet etching requires the metal design rules to be large. Therefore, multiple gate buses in a conventional power MOSFET consume a large area of the semiconductor die, which could otherwise be used for the active part of the device.

"When a power MOSFET is configured for flip-mounting onto conductive pads using solder or the like additional issues further lead to the inefficient use of semiconductor area. For example, the gate pad required for flip-mounting is large compared with a wire-bonded device, which wastes more semiconductor area that could be used for the active region of the device. In addition, the layout of a large source pad required for flip-mounting may restrict the use of multiple gate buses."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "In a power semiconductor according to the present invention the thick metal layer in a conventional device is replaced by a thin metal layer (e.g. 1-2 .mu.m) which can be dry etched. The thin metal layer is then patterned to obtain a metallic gate bus that is then preferably encapsulated in a hermetic seal, followed by formation of a thick stress relieving buffer body. The buffer body allows the deposition of a thick (e.g. 4-20 .mu.m) second metal layer to be added by preventing stress-related cracking of the hermetic seal during reliability testing such as temperature cycling. The thick second metal layer, which is thick enough to carry current as required by a power semiconductor device, can be then wet etched.

"Advantageously, the thick second metal layer can be thicker than conventional front metal bodies in that no gate buses are required to be patterned out of the same.

"Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings."

URL and more information on this patent, see: Montgomery, Robert; Burke, Hugo; Parsonage, Philip; Johns, Susan; Jones, David Paul. Power Semiconductor Device Including a Double Metal Contact. U.S. Patent Number 8791525, filed February 25, 2008, and published online on July 29, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8791525.PN.&OS=PN/8791525RS=PN/8791525

Keywords for this news article include: Electronics, Semiconductor, International Rectifier Corporation.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


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Source: Electronics Newsweekly


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