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Findings from University of Tennessee in Computer Research Reported (DPPC: Dynamic Power Partitioning and Control for Improved Chip Multiprocessor...

August 14, 2014



Findings from University of Tennessee in Computer Research Reported (DPPC: Dynamic Power Partitioning and Control for Improved Chip Multiprocessor Performance)

By a News Reporter-Staff News Editor at Computer Weekly News -- Investigators publish new report on Computer Research. According to news originating from Knoxville, Tennessee, by VerticalNews correspondents, research stated, "A key challenge in chip multiprocessor (CMP) design is to optimize the performance within a power budget limited by the CMP's cooling, packaging, and power supply capacities. Most existing solutions rely solely on dynamic voltage and frequency scaling (DVFS) to adapt the power consumption of CPU cores, without coordinating with the last-level on-chip (e.g., L2) cache."

Our news journalists obtained a quote from the research from the University of Tennessee, "This paper proposes DPPC, a chip-level power partitioning and control strategy that can dynamically and explicitly partition the chip-level power budget among different CPU cores and the shared last-level cache in a CMP based on the workload characteristics measured online. DPPC features a novel performance-power model and an online model estimator to quantitatively estimate the performance contributed by each core and the cache with their respective local power budgets. DPPC then re-partitions the chip-level power budget among them for optimized CMP performance. The partitioned local power budgets for the CPU cores and cache are precisely enforced by power control algorithms designed rigorously based on feedback control theory."

According to the news editors, the research concluded: "Our extensive experimental results demonstrate that DPPC achieves better CMP performance, within a given power budget, than several state-of-the-art power control solutions for both SPEC CPU2006 benchmarks and multi-threaded SPLASH-2 workloads."

For more information on this research see: DPPC: Dynamic Power Partitioning and Control for Improved Chip Multiprocessor Performance. IEEE Transactions on Computers, 2014;63(7):1736-1750. IEEE Transactions on Computers can be contacted at: Ieee Computer Soc, 10662 Los Vaqueros Circle, PO Box 3014, Los Alamitos, CA 90720-1314, USA. (Institute of Electrical and Electronics Engineers - www.ieee.org/; IEEE Transactions on Computers - ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12)

The news correspondents report that additional information may be obtained from K. Ma, University of Tennessee, Dept. of Elect Engn & Comp Sci, Knoxville, TN, United States. Additional authors for this research include X.R. Wang and Y.F. Wang.

Keywords for this news article include: Knoxville, Tennessee, United States, Computer Research, North and Central America

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


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Source: Computer Weekly News


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