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Researchers Submit Patent Application, "Three-Dimensional Semiconductor Memory Device", for Approval

September 3, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors PARK, Sang-Yong (Suwon-si, KR); PARK, Jintaek (Hwaseong-si, KR), filed on April 17, 2014, was made available online on August 21, 2014.

The patent's assignee is Samsung Electronics Co., Ltd.

News editors obtained the following quote from the background information supplied by the inventors: "Embodiments of the inventive concept relate generally to a semiconductor device, and more particularly, to a three-dimensional semiconductor memory device including three-dimensionally arranged memory cells and methods of fabricating the same.

"A three-dimensional integrated circuit (3D-IC) memory technique may be used to increase a memory capacity. The 3D-IC memory technique generally refers to technology related to arranging memory cells three-dimensionally.

"One 3D-IC technique is a punch-and-plug technique. The punch-and-plug technique includes sequentially forming multi-layered thin layers on a substrate and then forming plugs to penetrate the thin layers. Through this technique, without a drastic increase of manufacturing costs, a three-dimensional memory device may obtain an increased memory capacity."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "Example embodiments of the inventive concept may provide a three-dimensional (3D) semiconductor device with a large memory capacity.

"Example embodiments of the inventive concept may also provide a 3D semiconductor device including a plurality of stacked structures and having a reduced pad region area.

"According to example embodiments of the inventive concept, a three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure.

"The device may further include bit lines electrically connecting the vertical channel structures with each other, the bit lines extending along the first direction.

"The stacked structure may further include insulating layers interposed between the conductive layers, sidewalls of the conductive layers and the insulating layers exposed in the first direction are substantially coplanar with each other.

"Widths of the plurality of conductive layers along the first direction may be substantially the same.

"The conductive layers may include first pads, each first pad being exposed by a sequentially stacked conductive layer and being spaced apart from the vertical structures along the second direction.

"The device may further include contact plugs disposed on the respective first pads.

"The conductive layers may include second pads, each second pad being exposed by a sequentially stacked conductive layer and being spaced apart from the vertical structures along the first direction.

"A width of the second pad along the first direction may be smaller than a width of the first pad along the second direction.

"A distance along a third direction between sidewalls of the upper and lower of the conductive layers may be smaller than a distance along the second direction between sidewalls of the upper and lower of the conductive layer, the third direction being opposite the second direction.

"A distance from the vertical channel structure to an edge of the stacked structure may be smaller in the first direction than in the second direction.

"According to other example embodiments of the inventive concept, a three-dimensional semiconductor device includes a first stacked structure on a substrate, the first stacked structure including a first memory region penetrated by a first vertical channel structure and a first pad region adjacent the first memory region, and a second stacked structure on the first stacked structure, the second stacked structure including a second memory region penetrated by a second vertical channel structure and a second pad region adjacent the second memory region, wherein in a plan view, major axes of the first and second stacked structures cross each other.

"A distance between the first memory region and an edge of the first pad region may be smaller in a first direction parallel to a top surface of the substrate than in a second direction crossing the first direction, and a distance between the second memory region and an edge of the second pad region may be greater in the first direction than in the second direction.

"The distance between the first memory region and the edge of the first pad region may be smaller in a direction opposite the second direction than in the second direction, and the distance between the second memory region and the edge of the second pad region may be smaller in a direction opposite the first direction than in the first direction.

"A width of the first stacked structure along the first direction may be smaller than a width of the second stacked structure along the first direction, and a width of the first stacked structure along the second direction may be greater than a width of the second stacked structure along the second direction.

"The device may further include an interlayer insulating layer interposed between the first pad region and the second stacked structure.

"According to yet other example embodiments of the inventive concept, a three-dimensional semiconductor device includes a first stacked structure including a plurality of conductive layers stacked on a substrate, the stacked structure including a memory region and at least one pad region adjacent a first side of the memory region along a first direction, a vertical channel structure penetrating the conductive layers in the memory region, and pads on the conductive layers in the pad region, wherein a distance along the first direction between sidewalls of sequentially arranged conductive layers is larger than a distance along a second direction between sidewalls of the sequentially arranged conductive layers, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate.

"Each conductive layer may include a first sidewall substantially extending along the first direction, and a second sidewall substantially extending along the second direction, first sidewalls of at least two sequentially stacked conductive layers of the plurality of conductive layers being aligned with each other to define a uniform flat plane of the memory region, the flat plane being at a side of the memory region other than the first side.

"The pads and the memory region may be adjacent to each other only along the first direction.

"The first sidewalls of all the stacked conductive layers may be aligned with each other to define a uniform flat plane of the memory region, the flat plane being at a side of the memory region other than the first side.

"The device may further include a second stacked structure on the first stacked structure, the second stacked structure having a vertical channel structure in a memory region and pads on conductive layers in a pad region, major axes of the first and second stacked structures crossing each other.

BRIEF DESCRIPTION OF THE DRAWINGS

"The above and other features and advantages will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments with reference to the attached drawings, in which:

"FIG. 1 illustrates a circuit diagram of a three dimensional (3D) semiconductor memory device according to embodiments of the inventive concept;

"FIGS. 2 and 3 illustrate schematic planar and cross-sectional views, respectively, of a 3D semiconductor device according to a first embodiment of the inventive concept;

"FIGS. 4 through 11 illustrate methods of fabricating a 3D semiconductor device according to a first embodiment of the inventive concept;

"FIGS. 12 and 13 illustrate schematic planar and cross-sectional views, respectively, of a 3D semiconductor device according to modifications of the first embodiments of the inventive concept;

"FIGS. 14 and 15 illustrate schematic planar and cross-sectional views, respectively, of a 3D semiconductor device according to a second embodiment of the inventive concept;

"FIGS. 16 and 17 illustrate methods of fabricating a 3D semiconductor device according to a second embodiment of the inventive concept;

"FIGS. 18 and 19 illustrate schematic planar and cross-sectional views, respectively, of a 3D semiconductor device according to a third embodiment of the inventive concept;

"FIGS. 20 through 29 illustrate methods of fabricating a 3D semiconductor device according to a third embodiment of the inventive concept;

"FIG. 30 illustrates a flowchart of methods of fabricating a 3D semiconductor device according to a third embodiment of the inventive concept;

"FIGS. 31 and 32 illustrate schematic planar and cross-sectional views, respectively, of a 3D semiconductor device according to a fourth embodiment of the inventive concept;

"FIGS. 33 through 42 illustrate methods of fabricating a 3D semiconductor device according to a fourth embodiment of the inventive concept;

"FIGS. 43 through 45 illustrate a 3D semiconductor device and methods of fabricating according to a fifth embodiment of the inventive concept;

"FIGS. 46 through 48 illustrate a 3D semiconductor device and methods of fabricating the same according to modifications of the fifth embodiment of the inventive concept;

"FIG. 49 illustrates methods of fabricating conductive layers according to example embodiments of the inventive concept;

"FIGS. 50 through 52 illustrate methods of fabricating the stacked structures;

"FIG. 53 illustrates a schematic block diagram of an example of a memory system including a semiconductor memory device according to some embodiments of the inventive concept;

"FIG. 54 illustrates a block diagram of an example of a memory card including a semiconductor memory device according to some embodiments of the inventive concept; and

"FIG. 55 illustrates a block diagram of an example of an information processing system including a semiconductor memory device according to some embodiments of the inventive concept.

"It should be noted that these figures are intended to illustrate the general characteristics of methods, structure and/or materials utilized in certain example embodiments and to supplement the written description provided below. These drawings are not, however, to scale and may not precisely reflect the precise structural or performance characteristics of any given embodiment, and should not be interpreted as defining or limiting the range of values or properties encompassed by example embodiments. For example, the relative thicknesses and positioning of molecules, layers, regions and/or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numbers in the various drawings is intended to indicate the presence of a similar or identical element or feature."

For additional information on this patent application, see: PARK, Sang-Yong; PARK, Jintaek. Three-Dimensional Semiconductor Memory Device. Filed April 17, 2014 and posted August 21, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4931&p=99&f=G&l=50&d=PG01&S1=20140814.PD.&OS=PD/20140814&RS=PD/20140814

Keywords for this news article include: Semiconductor, Samsung Electronics Co. Ltd..

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Source: Electronics Newsweekly


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