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Researchers Submit Patent Application, "Pattern Forming Method and Manufacturing Method of Semiconductor Device", for Approval

September 3, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors TAKEISHI, Tomoyuki (Kawasaki-shi, JP); KATO, Hirokazu (Yokohama-shi, JP); ITO, Shinichi (Yokohama-shi, JP), filed on April 22, 2014, was made available online on August 21, 2014.

The patent's assignee is Kabushiki Kaisha Toshiba.

News editors obtained the following quote from the background information supplied by the inventors: "The present invention relates to a pattern forming method for use in processing a substrate such as a semiconductor substrate, a glass substrate, and a resin substrate.

"Therefore, in a pattern exposure apparatus, high resolution is accelerated by producing short wavelengths with an excimer laser for use in KrF.fwdarw.ArF.fwdarw.F.sub.2. On the other hand, with more fining, pattern breakage of a resist film cannot be ignored.

"Therefore, a multilayer resist process for preventing pattern breakage by reducing the film thickness of a chemically amplified resist is used.

"For example, as described in Jpn. Pat. Appln. KOKAI Publication No. 6-84787, there has been a problem that an upper-layered resist pattern falls (is released) in a multilayer resist process. In Jpn. Pat. Appln. KOKAI Publication No. 6-84787, it has been reported that an SOG film surface is temporarily subjected to hydrophobic processing, and then, a chemically amplified resist is formed, thereby restricting release of the resist pattern. However, this method has proved insufficient, although a certain advantageous effect is attained in restricting the release of the resist pattern.

"As described above, in the multilayer resist process, there has been a problem that an upper-layered resist pattern is released/falls."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "According to an aspect of the present invention, there is provided a pattern forming method comprising: forming a spin on dielectric film on a substrate; washing the spin on dielectric film by using a washing liquid; drying a surface of the spin on dielectric film after the washing; forming a photosensitive film on the dried spin on dielectric film; emitting energy rays to a predetermined position of the photosensitive film in order to form a latent image on the photosensitive film; developing the photosensitive film in order to form a photosensitive film pattern which corresponds to the latent image; and processing the coating type insulation film with the photosensitive film pattern serving as a mask.

"According to another aspect of the present invention, there is provided a pattern forming method comprising: preparing a first substrate; forming a photosensitive film on the first substrate; washing the photosensitive film by using a first washing liquid; emitting energy rays to a predetermined position of the photosensitive film by using an immersion type exposure in order to form a latent image on the photosensitive film after washing the photosensitive film; developing the photosensitive film in order to form a photosensitive film pattern which corresponds to the latent image; and processing the first substrate with the photosensitive film pattern serving as a mask.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

"FIGS. 1A to 1G are sectional views each showing procedures in a pattern forming method according to a first embodiment;

"FIG. 2 is a sectional view schematically showing a pattern release when a pattern has been formed in a conventional three-layer resist process;

"FIGS. 3A to 3E are sectional views each showing procedures in a pattern forming method in a second embodiment;

"FIG. 4 is a view schematically showing a resist pattern breakage phenomenon which occurs due to shortage of resist strength; and

"FIGS. 5A to 5G are sectional views each showing procedures in a pattern forming method according to a third embodiment."

For additional information on this patent application, see: TAKEISHI, Tomoyuki; KATO, Hirokazu; ITO, Shinichi. Pattern Forming Method and Manufacturing Method of Semiconductor Device. Filed April 22, 2014 and posted August 21, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=3977&p=80&f=G&l=50&d=PG01&S1=20140814.PD.&OS=PD/20140814&RS=PD/20140814

Keywords for this news article include: Electronics, Semiconductor, Kabushiki Kaisha Toshiba.

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Source: Electronics Newsweekly


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