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Researchers Submit Patent Application, "Modulating Bow of Thin Wafers", for Approval

September 3, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Gambino, Jeffrey P. (Westford, VT); Hall, John C. (New Hartford, CT); McAvey, JR., Kenneth F. (Winooski, VT); Musante, Charles F. (Colchester, VT); Stamper, Anthony K. (Essex Junction, VT), filed on February 12, 2013, was made available online on August 21, 2014.

The patent's assignee is International Business Machines Corporation.

News editors obtained the following quote from the background information supplied by the inventors: "The present disclosure relates to fabrication of semiconductor devices. More particularly, the disclosure relates to methods for balancing stress in a wafer used to create semiconductor dies.

"An individual integrated circuit semiconductor die is usually formed from a larger structure known as a semiconductor wafer. A wafer is a thin slice of semiconductor material, such as a silicon crystal, used in the fabrication of integrated circuits and other microdevices. The wafer serves as the substrate for microelectronic devices built in and over the wafer and undergoes many microfabrication process steps. Each semiconductor wafer typically has a plurality of integrated circuits arranged in rows and columns with the periphery of each integrated circuit being rectangular. The front side or surface of the wafer is first ground and polished to a smooth surface, for fabrication of multiple integrated circuits thereon.

"Fabrication of the integrated circuits is performed on the active surface of the undivided wafer, and consists of various processes including known steps of layering, patterning, doping, etching, and heat treatment, for example. Various layers applied to the active surface of the wafer typically include insulators, semiconductors, and metallic conductors. The final layering step generally comprises the application of a passivation material to cover the integrated circuit with a smooth electrically insulative protective layer.

"Wafer thinning is performed in order to (a) reduce the package size, (b) reduce the consumption of saw blades in subsequent die singulation from the wafer, and remove any electrical junctions that have formed on the wafer back side during fabrication. The processes typically used for wafer thinning include mechanical grinding and chemical-mechanical polishing (CMP). Alternatively, etching may be used but is not generally preferred. Each of these processes requires protection of the front side or active surface of the wafer containing the electronic components of the semiconductor die and/or wafer.

"Although wafer thinning produces semiconductor dice of much reduced size, it also tends to result in a higher incidence of semiconductor die breakage. In addition, stresses induced by any grinding and polishing processes must be carefully controlled to prevent wafer and semiconductor die warping or bowing. Wafer warp interferes with precise semiconductor die separation (singulation), and semiconductor die warping results in die-attach problems in subsequent packaging.

"Stresses introduced by the passivation layer may be sufficient to produce undesirable warping in the semiconductor dice, particularly where the wafer has been thinned to a high degree."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "According to an apparatus herein, a wafer comprises semiconductor material. The wafer has a front side and a back side. A plurality of circuits comprising individual semiconductor devices are formed on the front side of the wafer. A stress-balancing layer is on the back side of the wafer. The stress-balancing layer comprises either a polymeric film or a metal film having at least one metal layer. The stress-balancing layer provides an in-situ bilateral tensile stress in the stress-balancing layer as a result of a heat treatment to the wafer that modulates the bowing of thin wafers.

"According to a method herein, a wafer is formed of semiconductor material. The wafer has a front side and a back side. A cross-section of the wafer is reduced by thinning material from the front side of the wafer. A plurality of circuits comprising individual semiconductor devices is formed on the front side of the wafer. A stress-balancing layer is formed on the back side of the wafer. The stress-balancing layer comprises either a polymeric film or a metal film having at least one metal layer. A heat treatment is applied to the wafer. The heat treatment develops an in-situ bilateral tensile stress in the stress-balancing layer.

"According to another method herein, a wafer is formed of semiconductor material. The wafer has a front side and a back side. A cross-section of the wafer is reduced by thinning material from the front side of the wafer. A film is deposited on a back side of the wafer. A heat treatment is applied to the wafer. The heat treatment develops an in-situ bilateral tensile stress in the film.

"According to another method herein, a stress-balancing layer is formed on a back side of a semiconductor wafer. The semiconductor wafer comprises a plurality of individual semiconductor circuits on a front side of the wafer. The stress-balancing layer comprises at least one of a polymer film and a metal film having at least one metal layer. The wafer is annealed to a temperature between 150.degree. C. and 450.degree. C.

BRIEF DESCRIPTION OF THE DRAWINGS

"The devices and methods herein will be better understood from the following detailed description with reference to the drawings, which are not necessarily drawn to scale and in which:

"FIG. 1 is a cross-sectional view of a wafer illustrating the effect of process films on wafer bow;

"FIG. 2 is a cross-sectional view of a wafer according to devices and methods herein;

"FIG. 3 is a cross-sectional view of a wafer according to devices and methods herein;

"FIG. 4 is a cross-sectional view of a wafer according to devices and methods herein;

"FIG. 5 is a chart illustrating wafer bow as a function of anneal temperature; and

"FIG. 6 is a flow diagram illustrating methods herein."

For additional information on this patent application, see: Gambino, Jeffrey P.; Hall, John C.; McAvey, JR., Kenneth F.; Musante, Charles F.; Stamper, Anthony K. Modulating Bow of Thin Wafers. Filed February 12, 2013 and posted August 21, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4883&p=98&f=G&l=50&d=PG01&S1=20140814.PD.&OS=PD/20140814&RS=PD/20140814

Keywords for this news article include: Electronics, Semiconductor, International Business Machines Corporation.

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Source: Electronics Newsweekly


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