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Researchers Submit Patent Application, "Method for Producing Structured Sintered Connection Layers, and Semiconductor Element Having a Structured...

September 3, 2014



Researchers Submit Patent Application, "Method for Producing Structured Sintered Connection Layers, and Semiconductor Element Having a Structured Sintered Connection Layer", for Approval

By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Guyenot, Michael (Ludwigsburg, DE); Guenther, Michael (Stuttgart, DE); Herboth, Thomas (Ludwigsburg, DE), filed on June 26, 2012, was made available online on August 21, 2014.

No assignee for this patent application has been made.

News editors obtained the following quote from the background information supplied by the inventors: "Electronic components such as power diodes, (vertical) power transistors or other components must be mounted on substrates. Because of the high currents through such components, it is important to ensure excellent electric and thermal coupling between the components and the substrate.

"It is possible to use sintered connections on silver basis (silver sintering) for the mechanical connection between semiconductors and metallic layers, e.g., copper layers, such as the Low-Temperature Connection Technology of Power Electronics (Fortschritt Reports of the VDI, series 21, No. 365, VDI-Verlag), and related methods. In silver sintering, a paste including micro particles or nano particles is compressed under increased temperature and increased pressure; during this process the individual particles coalesce to form a mechanically stable sinter layer and establish a stable mechanical connection between two components abutting the sinter layer.

"Because of the different coefficients of thermal expansion of semiconductors and metallic layers, mechanical warping may occur in the sinter layer, which could have an adverse effect on the stability and reliability of the sinter layer.

"The printed publication EP 2 075 835 A2 discusses methods for developing sinter layers between a semiconductor chip and a substrate, which can be used to improve the mechanical stability in that the sinter layer is set apart from the edges of the semiconductor chip and interspaces are developed between individual sinter sections."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "In one specific embodiment, the present invention provides a method for producing a sinter layer; the method includes the steps of applying a multitude of sinter elements from a base material forming the sinter layer in structured manner on a contact area of a main surface of a substrate; placing a chip to be bonded to the substrate on the sinter elements; and heating and compressing the sinter elements in order to produce a structured sinter layer that connects the substrate and the chip and extends within the contact area, the surface coverage density of the sinter elements on the substrate in a center region of the contact area being greater than the surface coverage density of the sinter elements in an edge region of the contact surface; furthermore, at least one through channel, which extends laterally with respect to the main surface of the substrate, is provided from each sintered element towards the edge of the contact surface.

"According to another specific embodiment, the present invention provides a semiconductor component, especially a power electronics semiconductor component, having a substrate with a main surface, a semiconductor chip disposed on the main surface of the substrate, and a structured sinter layer, which is situated between the substrate and the semiconductor chip on a contact area of the main surface and connects the chip to the substrate; the sinter layer includes a multitude of sinter elements whose surface coverage density on the substrate in a center region of the contact area is greater than the surface coverage density of the sinter elements in an edge region of the contact area; furthermore, at least one through channel, which extends laterally to the main surface of the substrate, is provided between the substrate and the chip toward the edge of the contact area.

"One basic aspect of the present invention is the production of a sinter layer connection between a substrate and a chip which produces a satisfactory electric and thermal connection between the substrate and the chip and also reduces mechanical tensions within the chip. This is achieved by a sinter layer made up of a multitude of sinter elements, which are placed in structured manner between the substrate and chip produced from a contact area. Because of a higher surface coverage density of the sinter elements in the center of the contact area it is possible to ensure excellent thermal and electrical conductivity in the particular locations where high temperatures typically develop when the chip is in operation. The surface coverage density of the sinter elements at the edge of the contact area is lower than in the center, so that the compression pressure there on each sinter element during the sintering process is effectively higher than in the center, which enhances the reliability of the sinter connection in the edge region.

"A through channel to each sinter element is formed along the main surface of the substrate between chip and substrate, so that gassing and degassing is ensured for all sinter elements during the sintering process. In particular the oxygen supply, which is required for adequate sintering, is able to be ensured via the through channels for each sinter element. At the same time, the gases emitted by the sinter elements during the sintering process are able to be discharged via the through channels, so that a uniform and predictable development of the sinter layer in all regions of the contact area is advantageously possible.

"In an advantageous manner, many sinter elements are able to be formed in the edge region, in particular, so that the entire thermal or electrical conductivity of the sinter layer will not be adversely affected even if individual sinter connections fail during or after the sintering operation, i.e., if there is a lack in thermal or electrical conductivity across individual sinter elements, because other sinter elements in the edge region are able to assume the function of the malfunctioning sinter elements.

"It may be advantageous to gradually increase the surface coverage density of the sinter elements on the substrate in a region of the contact area between the center region and edge region, from the surface coverage density in the edge region toward the surface coverage density in the center region of the contact area.

"The edge of the contact area in the lateral direction along the main surface of the substrate may advantageously be set apart from the edges of the chip by a predefined length. This may advantageously reduce mechanical stressing of the fracture-prone chip edge.

"In addition, it may be advantageous to select a larger lateral extension of the sinter elements in the center region of the contact area, in comparison with the lateral extension of the sinter elements in the edge region of the contact area. For one, this achieves a high surface coverage density in the mechanically less stressed center region of the contact area, which therefore results in improved thermal and electrical contacting of the sinter layer with the chip. For another, because of the lower surface coverage density in the edge region, the effective sinter pressure on each of the smaller sinter elements is increased in the edge region, which means that there is greater reliability of the sintering process and of the stability of the sinter connection in the mechanically heavily stressed edge region of the contact area.

"Advantageous developments constitute the subject matter of the respective further descriptions herein.

"The above embodiments and developments may be combined as desired if such a combination appears useful. Additional possible embodiments, developments and implementations of the present invention also include combinations of features of the present invention not explicitly mentioned above or below with regard to the exemplary embodiments.

"Further features and advantages of specific embodiments of the present invention result from the following description with reference to the enclosed drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

"FIG. 1a to 1c show schematic representations of the stages of a method for producing a structured sinter layer on a substrate according to one specific embodiment of the present invention.

"FIG. 2 shows a schematic representation of a component having structured sinter layers according to another specific embodiment of the present invention.

"FIG. 3 shows a schematic representation of a component having structured sinter layers according to another specific embodiment of the present invention.

"FIG. 4 shows a schematic representation of the surface structuring of a component having a sinter layer according to another specific embodiment of the present invention.

"FIG. 5 shows a schematic representation of the surface structuring of a component having a sinter layer according to another specific embodiment of the present invention."

For additional information on this patent application, see: Guyenot, Michael; Guenther, Michael; Herboth, Thomas. Method for Producing Structured Sintered Connection Layers, and Semiconductor Element Having a Structured Sintered Connection Layer. Filed June 26, 2012 and posted August 21, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4840&p=97&f=G&l=50&d=PG01&S1=20140814.PD.&OS=PD/20140814&RS=PD/20140814

Keywords for this news article include: Patents, Electronics, Semiconductor.

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Source: Electronics Newsweekly


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