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Researchers Submit Patent Application, "Memory Device and Corresponding Reading Method", for Approval

September 3, 2014

By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventor TORTI, CESARE (PAVIA, IT), filed on April 18, 2014, was made available online on August 21, 2014.

The patent's assignee is Stmicroelectronics S.r.l.

News editors obtained the following quote from the background information supplied by the inventors: "The non-volatile electrically erasable and programmable memory devices--also identified by the acronym EEPROM, 'Electrically Erasable Programmable Read Only Memory'--have reached a widespread use in the electronic applications market (from the industrial to the consumer level). Such a wide use is due to special features, such as the ability of retaining information without power supply, allowing the editing of the information thereof, and providing greater reliability than other storage devices, such as magnetic disk storage devices.

"The flash memory devices are, currently, the most widespread type of EEPROM devices in that, besides the features above mentioned, they have a very high storage capacity and present at the same time very reduced dimensions.

"The memory cells of a flash device may be arranged in a matrix according to a NOR architecture or a NAND architecture. In short, in a NOR architecture the memory cells of the same column of the matrix are connected in parallel to a same column line--or 'bit line'--while in a NAND architecture groups of memory cells of the same column of the matrix are connected to each other in series in order to form respective strings, which are then connected in parallel to one another to a same bit line.

"The matrix of memory cells of the flash memory devices of the NOR type can be structured according to a column-hierarchy. In this case, the columns of memory cells of the matrix are divided into clusters, each of which consists of a determined number of columns of memory cells. The memory cells of each column are associated with a respective local bit line, while each column cluster is associated with a respective main bit line. During a reading operation, a local bit line for each cluster is selected by selectively coupling it to the corresponding main bit line. In addition, a selected group of main bit lines is selectively coupled to suitable circuitry for the reading of data stored in the memory cells (sense amplifier). Consequently, during a reading operation, each sense amplifier is associated with a corresponding selected local bit line belonging to the selected clusters.

"The parasitic capacitances of the local bit lines and of the main bit lines are typically discharged to the ground voltage and then pre-charged to a suitable voltage level before each reading operation. However, the parasitic capacitance of a main bit line has a big entity, since the main bit lines are typically provided with a relatively high length and width, higher than those of the local bit line. Therefore, the time required to discharge and then pre-charge such capacitances is not negligible, and thus increases the overall duration of the reading operation, greatly reducing the performance of the memory device.

"During a reading operation, main bit lines are typically pre-charged and discharged in parallel. Given the non-negligible entity of the parasitic capacitances associated with each main bit line, such discharge and pre-charge operations involves as a whole the moving a large amount of charge, implying peaks of power consumption that would result in an effort for the supply circuits of the device, a temperature increase thereof, and above all, electromagnetic emissions that reduce the electromagnetic compatibility of the memory device.

"The electronics industry has proposed several solutions to overcome the abovementioned drawbacks. A known technique provides for the reduction of the length of the main bit lines--thereby reducing the capacitance associated with it and the structure of the main bit lines according to a hierarchical solution, where more main bit lines are selectively connectable to a respective global bit line connected to a respective global sense amplifier. Such global bit line will be discharged and pre-charged with different timing than the main bit lines and the local bit lines, thereby distributing the power consumption over time and thus lowering the consumption peak. However, such a solution has a significant cost in terms of area and realization complexity.

"A further solution is presented in the article 'A 0.13 .mu.m 2.125 MB 23.5 ns Embedded Flash with 2 GB/s Throughput for Automotive Microcontrollers' by Deml, Jankowski and Thalmaier (IEEE, ISSCC 2007, Session 26, Non-Volatile Memories, 26.4) in which is provided to maintain to a pre-charge voltage local bit lines and corresponding reference lines (source line) using an apposite pre-charge circuit. Upon selection, the pre-charge circuit is isolated from the local bit line and the corresponding source line. The source line is connected to a reference terminal, while the local bit line is connected to the sense amplifier through the main bit line. The capacitive coupling between the source line that is discharged and the local bit line causes a small change in voltage on the local bit line that is quickly attenuated by the sense amplifier.

"A still further solution is presented in the U.S. Pat. No. 7,236,403 wherein is described a pre-charge arrangement for the reading operation of integrated non-volatile memories having at least one memory cell, at least one source line, at least one bit line, at least one sense amplifier and at least a pre-charge potential. The bit line constantly receives the pre-charge potential in a deselected state of the bit line, and the source line receives a predetermined reference potential, particularly a ground potential, in a selected state of the bit line."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventor's summary information for this patent application: "In general terms, one or more embodiments of the present invention are intended to provide a memory device capable of ensuring an extremely fast reading operation without incurring in the abovementioned drawbacks.

"More specifically, one embodiment provides an electrically erasable and programmable non-volatile memory device. The memory device includes a plurality of memory cells arranged in rows and columns. Each column of memory cells is associated with a respective local bit line. The local bit lines are divided into packets of local bit lines. Each packet of local bit lines is associated with a respective main bit line, in which each local bit line is selectively couplable to the respective main bit line by a corresponding selector. Each local bit line is selectively couplable to a reference terminal for receiving a reference voltage through a corresponding discharge selector.

"Each discharge selector is active when the memory device is in a standby state. The non-volatile memory device further includes biasing means or circuitry adapted to bias each main bit line to a pre-charge voltage during the operation of the memory device, and reading means or circuitry adapted to select and to access a group of memory cells during a reading operation. The reading means or circuitry includes selection means or circuitry adapted to select each local bit line associated with each memory cell of the group by activating the corresponding selector and disabling the corresponding discharge selector. The reading means or circuitry further includes measure means or circuitry adapted to measure currents that flow in the selected local bit line for the reading of data stored in the memory cells of the group.

"Another aspect of the present invention relates to a corresponding method for operating a memory device.


"Embodiments of the invention, as well as additional features and their advantages will be better understood with reference to the following detailed description, given merely by way of non-limiting example, to be read in conjunction with the attached figures (wherein corresponding elements are designated with the same or similar references and their explanation is not repeated for brevity). In this regard, it is expressly understood that the figures are not necessarily to scale (with some details that may be exaggerated and/or simplified) and, unless otherwise stated, they are simply used to conceptually illustrate the structures and procedures. In particular:

"FIG. 1 illustrates a principle block diagram of a portion of a flash memory according to an implementation known in the art;

"FIG. 2 shows a principle circuit diagram of a sense amplifier included in the circuit of FIG. 1 according to a known in the art implementation;

"FIG. 3 illustrates a principle block diagram of a portion of a flash memory wherein the solution according to an embodiment of the present invention may be implemented;

"FIG. 4 illustrates a principle block diagram of a selection unit of the memory of FIG. 3 according to an embodiment of the present invention, and

"FIG. 5 shows a trend over time of main signals of the flash memory according to an embodiment of the present invention during a reading operation."

For additional information on this patent application, see: TORTI, CESARE. Memory Device and Corresponding Reading Method. Filed April 18, 2014 and posted August 21, 2014. Patent URL:

Keywords for this news article include: Electromagnet, Stmicroelectronics S.r.l.

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Source: Electronics Newsweekly

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