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Researchers Submit Patent Application, "Charge Pump with a Power-Controlled Clock Buffer to Reduce Power Consumption and Output Voltage Ripple", for...

September 4, 2014



Researchers Submit Patent Application, "Charge Pump with a Power-Controlled Clock Buffer to Reduce Power Consumption and Output Voltage Ripple", for Approval

By a News Reporter-Staff News Editor at Politics & Government Week -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Wang, Kesheng (Milpitas, CA); Al-Shamma, Ali (San Jose, CA), filed on December 9, 2013, was made available online on August 21, 2014.

The patent's assignee is SanDisk 3D LLC.

News editors obtained the following quote from the background information supplied by the inventors: "Semiconductor memory is widely used in various electronic devices such as cellular telephones, digital cameras, personal digital assistants, mobile computing devices, and non-mobile computing devices. A non-volatile memory device (e.g., a flash memory device) allows information to be stored and retained even when the non-volatile memory device is not connected to a source of power (e.g., a battery). Non-volatile memory devices typically include two-dimensional arrays of non-volatile memory cells. The memory cells within a two-dimensional array form a single layer of memory cells and may be selected via control lines in the X and Y directions. Non-volatile memory devices may also include monolithic three-dimensional memory arrays in which multiple layers of memory cells are formed above a single substrate without any intervening substrates.

"Charge pumps use a switching process to provide a DC output voltage larger or lower than its DC input voltage. Charge pumps are used in many contexts. For example, they are used as peripheral circuits on non-volatile memories to generate many of the needed operating voltages, such as programming or erase voltages, from a lower power supply voltage. A number of charge pump designs, such as conventional Dickson-type pumps, are known in the art. But given the common reliance upon charge pumps, there is an ongoing need for improvements in pump design, particularly with respect to trying to save on current consumption."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "In a principle set of aspects, a charge pump system includes a charge pump circuit, regulation circuitry, an oscillator circuit and a number of clock buffer circuits. The charge pump circuit is connected to receive N pump clock signals and generate from these an output voltage, where N is an integer greater than or equal to one. The regulation circuitry is connected to receive the output voltage and generate a regulation signal based on the output voltage. The oscillator circuit provides N initial clock signals. N clock buffer circuits each receive a corresponding one of the initial clock signals and generate from it a corresponding one of the pump clock signals. Each of the buffer circuits includes: a plurality of inverters connected in series, with the first inverter in the series connected to receive the corresponding initial clock signal as input and the last inverter in the series providing the corresponding pump clock signal as output; and a corresponding plurality of clamp elements connected to receive the regulation signal and through which a corresponding one of the inverter is connected to a power supply level, the voltage level being supplied to the corresponding inverter being dependent upon the regulation signal.

"Various aspects, advantages, features and embodiments of the present invention are included in the following description of exemplary examples thereof, which description should be taken in conjunction with the accompanying drawings. All patents, patent applications, articles, other publications, documents and things referenced herein are hereby incorporated herein by this reference in their entirety for all purposes. To the extent of any inconsistency or conflict in the definition or use of terms between any of the incorporated publications, documents or things and the present application, those of the present application shall prevail.

BRIEF DESCRIPTION OF THE DRAWINGS

"FIG. 1A depicts one embodiment of a memory system.

"FIG. 1B depicts one embodiment of memory core control circuits.

"FIG. 1C depicts one embodiment of a memory core.

"FIG. 1D depicts one embodiment of a memory bay.

"FIG. 1E depicts one embodiment of a memory block.

"FIG. 1F depicts another embodiment of a memory bay.

"FIG. 2A depicts one embodiment of a schematic diagram corresponding with the memory bay of FIG. 1F.

"FIG. 2B depicts one embodiment of a schematic diagram corresponding with a memory bay arrangement wherein word lines and bit lines are shared across memory blocks, and both row decoders and column decoders are split.

"FIG. 3A depicts one embodiment of a portion of a monolithic three-dimensional memory array.

"FIG. 3B depicts one embodiment of a portion of a monolithic three-dimensional memory array that includes a second memory level positioned above a first memory level.

"FIG. 3C depicts a subset of the memory array and routing layers of one embodiment of a three-dimensional memory array.

"FIG. 4 depicts one embodiment of a portion of a monolithic three-dimensional memory array.

"FIG. 5 depicts one embodiment of a read/write circuit along with a portion of a memory array.

"FIG. 6A depicts one embodiment of a cross-point memory array.

"FIG. 6B depicts an alternative embodiment of a cross-point memory array.

"FIG. 7A depicts one embodiment of memory cell current distributions for memory cells programmed into an ON state and memory cells programmed into an OFF state over an applied memory cell voltage.

"FIG. 7B depicts one embodiment of memory cell current distributions for memory cells programmed into an ON and memory cells programmed into an OFF state for a given memory cell bias voltage applied to the memory cells.

"FIG. 8A depicts one embodiment of circuitry for generating a plurality of bit line voltage options.

"FIG. 8B depicts one embodiment of a VSFG generator.

"FIG. 8C depicts one embodiment of a read/write circuit.

"FIG. 8D depicts one embodiment of a portion of a memory core.

"FIG. 9A is a flowchart describing one embodiment of a process for programming a memory cell.

"FIG. 9B is a flowchart describing one embodiment of a process for generating a plurality of bit line voltages associated with different compensation options.

"FIG. 9C is a flowchart describing one embodiment of a process for determining whether a memory cell has characteristics of a strong memory cell, a weak memory cell, or a typical memory cell.

"FIG. 9D is a flowchart describing one embodiment of a process for reading a memory cell.

"FIG. 10 is a simplified top-level block diagram of a typical charge pump using an output voltage based regulation scheme.

"FIG. 11 is a charge pump system using a gated clock strategy.

"FIG. 12 is a charge pump system using an adjustable clock frequency regulation strategy.

"FIG. 13 illustrates gated clock regulation ripple.

"FIG. 14 illustrates inverter switching in a clock buffer.

"FIG. 15 shows a pump clock regulated by a gated clock strategy.

"FIG. 16 illustrates adjustable clock regulation ripple.

"FIG. 17 shows a pump clock regulated by an adjustable clock strategy.

"FIGS. 18A-C are examples of level controller inverters.

"FIG. 19 illustrate regulating of the clock buffer output voltage.

"FIG. 20 illustrates an exemplary embodiment of a charge pump system.

"FIG. 21 shows the relation between pump output and pump clock amplitude for the embodiment of FIG. 20.

"FIG. 22 shows output ripple for the embodiment of FIG. 20.

"FIG. 23 looks at voltage level variation for a frequency fixed pump feed-in clock signal, such would be suitable for RF applications.

"FIG. 24 looks at voltage level variation for a frequency fixed pump feed-in clock signal, such would be suitable for low power applications."

For additional information on this patent application, see: Wang, Kesheng; Al-Shamma, Ali. Charge Pump with a Power-Controlled Clock Buffer to Reduce Power Consumption and Output Voltage Ripple. Filed December 9, 2013 and posted August 21, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4462&p=90&f=G&l=50&d=PG01&S1=20140814.PD.&OS=PD/20140814&RS=PD/20140814

Keywords for this news article include: Legal Issues, SanDisk 3D LLC.

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