News Column

"Reducing Deterioration in Display Quality of a Displayed Image on a Display Device" in Patent Application Approval Process

September 4, 2014



By a News Reporter-Staff News Editor at Politics & Government Week -- A patent application by the inventors NAKANISHI, Hideyuki (Osaka, JP); OOISHI, Yoshihisa (Osaka, JP); YAMAZAKI, Sachiko (Osaka, JP), filed on February 7, 2014, was made available online on August 21, 2014, according to news reporting originating from Washington, D.C., by VerticalNews correspondents.

This patent application is assigned to Panasonic Liquid Crystal Display Co., Ltd.

The following quote was obtained by the news editors from the background information supplied by the inventors: "A liquid crystal display device or the like is used as the display device of high resolution color monitors of computers and other information equipment, or television receivers. The liquid crystal display device fundamentally includes a display portion in which liquid crystals are sandwiched between two substrates at least one of which is made of transparent glass or the like. In addition, the liquid crystal display device includes a driver for selectively applying voltages to pixel electrodes formed on the substrate of the display portion. Pixels of the respective pixel electrodes are controlled based on voltage application by the driver.

"The display portion generally includes a plurality of gate signal lines, a plurality of source signal lines, and a plurality of pixel electrodes. The gate signal lines, for instance, extend in a horizontal direction (main scanning direction), and are aligned in a vertical direction (sub scanning direction). The source signal lines, for instance, extend in the vertical direction (sub scanning direction), and are aligned in the horizontal direction (main scanning direction). A plurality of thin film transistors (TFTs) and the pixel electrodes are disposed in a matrix at intersection points of the gate signal lines and the source signal lines. The gate driver outputs voltages (gate signals) to the gate signal lines for turning on and off the TFTs. Moreover, the source driver outputs voltages (source signals) based on an input image signal to the pixel electrodes via the source signal lines, thereby controlling transmittance of the liquid crystals provided corresponding to the pixel electrodes to values according to the source signals.

"In the display device, for instance, based on the external input image signal, frame images displayed on the display portion are sequentially switched to display a smooth image on the display portion. For a frame frequency, which is a frequency at which the frame images are switched, 60 Hz is generally used. JP-A-2003-280578 describes a display device that detects whether the input image signal is a signal representing a still picture or a moving picture and switches a frame frequency in accordance with a detection result. In the device described in JP-A-2003-280578, when the input image signal represents a still picture, the frame frequency is lowered to reduce power consumption at the time of image display.

"The source signals based on the input image signal are applied to the pixel electrodes while the gate signals are on. When the gate signals are turned off, ideally, voltages applied to the pixel electrodes are maintained, so that brightness of the pixels is kept at a certain value. However, since the voltages can leak from the pixel electrodes, the brightness of the pixels decreases while the gate signals are off.

"FIG. 8 is a diagram schematically showing the pixel corresponding to the gate signal line in a display screen. FIG. 9 is a timing chart schematically showing the brightness of the pixel when the frame frequency is 60 Hz. FIG. 10 is a timing chart schematically showing the brightness of the pixel when the frame frequency is 15 Hz.

"The brightness of a pixel P corresponding to a gate signal line Gb in a display screen 120 shown in FIG. 8 fluctuates, as shown in FIGS. 9 and 10. When the frame frequency is 60 Hz, which is relatively high, a fluctuation range of the brightness is small, as shown in FIG. 9. Accordingly, flicker caused by the fluctuation of the brightness may be inconspicuous. On the other hand, when the frame frequency is 15 Hz, which is low, the fluctuation range of the brightness is larger than the case of FIG. 9, as shown in FIG. 10. Accordingly, the flicker caused by the fluctuation of the brightness may be conspicuous.

"In general, in the display device, the gate signals are outputted to the gate signal lines in array order of the gate signal lines, for instance, from the gate signal line at an upper end to the gate signal line at a lower end. In the above-described display device, when the frame frequency is lowered, there are a method of expanding a vertical blanking period and a method of providing a horizontal blanking period.

"FIG. 11 is a timing chart schematically showing the gate signals and the brightness when the frame frequency is lowered by expanding the vertical blanking period. In FIG. 11, section (A) indicates gate signals of gate signal lines G1 to G16, and section (B) indicates the brightness of the pixels of the gate signal lines G1 to G4, and section (C) indicates the brightness of the pixels of the gate signal lines G9 to G12.

"As shown in section (A) of FIG. 11, a vertical blanking period V0 when the frame frequency is 60 Hz is expanded to V1, thereby lowering the frame frequency to 15 Hz. In this case, as shown in sections (B) and (C) of FIG. 11, the brightness of the whole display screen rises in a period in which the gate signals are outputted, and the brightness of the whole display screen gradually decreases in the subsequent vertical blanking period V1. Accordingly, flicker in the whole display screen occurs.

"FIG. 12 is a timing chart schematically showing the gate signals and the brightness when the frame frequency is lowered by providing the horizontal blanking period. In FIG. 12, section (A) indicates the gate signals of the gate signal lines G1 to G16, and section (B) indicates the brightness of the pixels of the gate signal lines G1 to G4, and section (C) indicates the brightness of the pixels of the gate signal lines G9 and G10.

"As shown in section (A) of FIG. 12, a horizontal blanking period H1 is provided to thereby lower the frame frequency to 15 Hz. In this case, as shown in sections (B) and (C) of FIG. 12, the brightness of the gate signal lines G1 to G16 rises at regular intervals sequentially from top, and then gradually decreases. Accordingly, flicker occurs so as to sequentially ripple from top to bottom of the display screen.

"As described above, when the frame frequency is lowered, whichever method of expanding the vertical blanking period or providing the horizontal blanking period is used, the flicker occurs, so that display quality of an image displayed on the display portion is deteriorated."

In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventors' summary information for this patent application: "In one general aspect, the instant application describe a display device that includes a display portion having a plurality of gate signal lines extending in a first direction and aligned in a second direction intersecting the first direction, a plurality of source signal lines extending in the second direction and aligned in the first direction, and a plurality of pixels connected to the source signal lines and the gate signal lines. The display portion is configured to display an image at a frame frequency for each frame. The display device further includes a gate driver configured to output gate signals to the gate signal lines sequentially and a source driver configured to output source signals to the pixels connected to the gate signal lines to which the gate signals are outputted, the source signals configured to display the image through the source signal lines. The display device further includes a controller configured to control the gate driver and the source driver to cause the display portion to display the image at the frame frequency for each frame. The controller sets the frame frequency to a first frame frequency F1 when the image is a moving picture, and the controller sets the frame frequency to a second frame frequency F2 lower than the first frame frequency F1 when the image is a still picture. The gate driver outputs the gate signals to the gate signal lines in the aligned order of the gate signal lines in the second direction when the frame frequency is the first frame frequency F1. The gate driver outputs the gate signals to the gate signal lines in a different order from the aligned order when the frame frequency is the second frame frequency F2.

BRIEF DSCRIPTION OF THE DRAWINGS

"FIG. 1 is a block diagram showing a configuration of a display device of one implementation of the present application.

"FIG. 2 is a circuit diagram showing a connection state of signal lines of a liquid crystal display panel shown in FIG. 1.

"FIG. 3 is a timing chart schematically showing an operation in the normal mode.

"FIG. 4 is a timing chart schematically showing an operation in the standby mode.

"FIG. 5 is a diagram schematically showing images displayed on the liquid crystal display panel.

"FIG. 6 is a timing chart schematically showing the gate drive signal outputted from the drive controller to the gate driver, and the gate signals outputted from the gate driver to the gate signal lines.

"FIG. 7 is a diagram schematically showing a generation method of the image control signal outputted from the signal processor to the source driver.

"FIG. 8 is a diagram schematically showing the pixel corresponding to the gate signal line in a display screen.

"FIG. 9 is a timing chart schematically showing the brightness of the pixel when the frame frequency is 60 Hz.

"FIG. 10 is a timing chart schematically showing the brightness of the pixel when the frame frequency is 15 Hz.

"FIG. 11 is a timing chart schematically showing the gate signals and the brightness when the frame frequency is lowered by expanding the vertical blanking period.

"FIG. 12 is a timing chart schematically showing the gate signals and the brightness when the frame frequency is lowered by providing the horizontal blanking period."

URL and more information on this patent application, see: NAKANISHI, Hideyuki; OOISHI, Yoshihisa; YAMAZAKI, Sachiko. Reducing Deterioration in Display Quality of a Displayed Image on a Display Device. Filed February 7, 2014 and posted August 21, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4237&p=85&f=G&l=50&d=PG01&S1=20140814.PD.&OS=PD/20140814&RS=PD/20140814

Keywords for this news article include: Panasonic Liquid Crystal Display Co. Ltd.

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Source: Politics & Government Week


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