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Patent Issued for Semiconductor Structure and Fabrication Method

September 3, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventors Tu, Shang-Hui (Tainan, TW); Tsai, Hung-Shern (Tainan County, TW), filed on May 16, 2012, was published online on August 19, 2014.

The patent's assignee for patent number 8809950 is Vanguard International Semiconductor Corporation (Hsinchu, TW).

News editors obtained the following quote from the background information supplied by the inventors: "The present invention relates to a semiconductor structure and fabrication method thereof.

"For current integrated circuit development, controllers, memories, low-voltage (LV) circuits and high-voltage (HV) power devices are being integrated into a single chip, referred to as a single-chip system. For example, to handle high voltage and current, double-diffused metal oxide semiconductor (DMOS) transistors, frequently used as conventional power devices, operate with low on-resistance while sustaining high voltage. Thus, lateral double-diffused metal oxide semiconductor (LDMOS) transistors in particular, with a simple structure, are being incorporated into VLSI logic circuits.

"However, the surface field of LDMOS transistors limits the voltage tolerance therein. Moreover, when operating an LDMOS device of an interdigitated structure, a high electric field occurring adjacent to the tip of a finger-shaped source results in decreased breakdown voltage of the device. Particularly, a high electric field, caused from scaling-down of related devices, decreasing device size as well as width of the source or curvature radius of the finger end, results in a very serious decrease of breakdown voltage. However, if the width of the finger shaped source is widened to enlarge the curvature radius of the finger end in order to increase the breakdown voltage and eliminate the problem mentioned above, layout flexibility of the device is sacrificed, thus hindering development for further scaling-down of related devices.

"An improved semiconductor device ameliorating the disadvantages of the conventional technology is desirable."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "A detailed description is given in the following embodiments with reference to the accompanying drawings.

"The invention provides a semiconductor structure and method for fabricating the same. In an embodiment of the method for fabricating the semiconductor structure, a first type doped body region is formed in a first type substrate. A first type heavily-doped region is formed in the first type doped body region. A second type well region and second type bar regions are formed in the first type substrate with the second type bar regions between the second type well region and the first type doped body region. The first type doped body region, the second type well region, and each of the second type bar regions are separated from each other by the first type substrate. The second type bar regions are inter-diffused to form a second type continuous region adjoining the second type well region. A second type heavily-doped region is formed in the second type well region.

"In an embodiment of the semiconductor structure of the present invention, a first type body doped region is disposed on the first type substrate. A first type heavily-doped region is disposed on the first type body doped region. A second type well region is disposed on the first type substrate. A plurality of second type bar regions is disposed between the second type well region and the first type body doped region. The first type body doped region, the second type well region, and each of the second type bar regions are separated to one another by the first type substrate. A second type heavily-doped region is disposed on the second type well region. An isolation structure is disposed on the first type substrate between the first type heavily-doped region and second type heavily-doped region. A gate structure is disposed on the first type substrate between the first type heavily-doped region and isolation structure.

"In another embodiment of the semiconductor structure, a first type body doped region is disposed on a first type substrate. A first type heavily-doped region is disposed on the first type body doped region. A second type well region is disposed on the first type substrate. A diffused second type well region is disposed between the second type well region and first type body doped region and adjoined to the second type well region. A second type impurity concentration of the diffused second type well region is lower than a second type impurity concentration of the second type well region. A second type heavily-doped region is disposed on the second type well region. An isolation structure is disposed on the diffused second type well region. A gate structure on the first type substrate is disposed between the first type heavily-doped region and isolation structure."

For additional information on this patent, see: Tu, Shang-Hui; Tsai, Hung-Shern. Semiconductor Structure and Fabrication Method. U.S. Patent Number 8809950, filed May 16, 2012, and published online on August 19, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8809950.PN.&OS=PN/8809950RS=PN/8809950

Keywords for this news article include: Electronics, High Voltage, Vanguard International Semiconductor Corporation.

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Source: Electronics Newsweekly


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