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Patent Issued for Semiconductor Memory Devices Including Vertical Transistor Structures

September 3, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- Samsung Electronics Co., Ltd. (KR) has been issued patent number 8809926, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventors are Kim, Sua (Seongnam-si, KR); Kim, Jin Ho (Uiwang-si, KR); Park, Chulwoo (Yongin-si, KR); Lee, Sangbo (Yongin-si, KR); Hwang, Hongsun (Suwon-si, KR).

This patent was filed on September 6, 2012 and was published online on August 19, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "Embodiments of inventive concepts relate generally to semiconductor devices, and more particularly, to semiconductor devices including vertical channel transistors.

"Due to small-size, multifunctional, and/or low-cost characteristics, semiconductor devices are considered important elements in the electronics industry. A semiconductor memory device is a type of semiconductor device configured to store and read out digitized data. Semiconductor devices may be classified as volatile memory devices or as nonvolatile memory devices. Volatile memory devices may lose stored data when power is interrupted. Volatile memory devices may, for example, include dynamic random access memory (DRAM) devices and static random access memory (SRAM) devices. Nonvolatile memory devices may maintain stored data even when power is interrupted. Nonvolatile memory devices may, for example, include FLASH memory devices.

"High capacity semiconductor Memory devices may be used to satisfy consumer demand for increased performance and reduced price. In the case of semiconductor memory devices, increased integration may be desired, because integration is a significant factor in determining product price. However, expensive process equipment that may be needed to reduce pattern dimensions may set a practical limit on increasing integration for semiconductor memory devices. To address such issues, there have been a variety of studies on new technologies to increase integration density of semiconductor memory devices."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "Embodiments of inventive concepts may provide increased density semiconductor memory devices.

"Other embodiments of inventive concepts may provide semiconductor memory devices with increased reliability.

"According to examples of embodiments of inventive concepts, a semiconductor memory device may include a common source region on a substrate, and an active pattern between the substrate and the common source region. The active pattern may include a first doped region and a second doped region, which may be spaced apart from each other in a direction normal to a top surface of the substrate. A channel region may be interposed between the first and second doped regions. A gate pattern may be disposed to face a sidewall of the active pattern, a gate dielectric pattern may be interposed between the gate pattern and the active pattern, a variable resistance pattern may be interposed between the common source region and the active pattern and connected to the second doped region, and an interconnection line may be connected to the first doped region.

"In some embodiments, the device may further include a conductive pattern facing another sidewall of the active pattern that may be opposite to the gate pattern.

"In some embodiments, the conductive pattern may be connected to the substrate.

"In some embodiments, the variable resistance pattern may be a magnetic tunnel junction.

"In some embodiments, the device may further include a word line connected to the gate pattern to cross the interconnection line.

"In some embodiments, the active pattern and the gate pattern may be provided as a plurality of active patterns and a plurality of gate patterns, and the active patterns and the gate patterns may be two-dimensionally arranged on the substrate along rows and columns, in a plan view. Each of the gate patterns may be disposed between the active patterns that may be adjacent to each other and parallel to the interconnection line. A pair of the active patterns may be disposed between a pair of the gate patterns that may be adjacent to each other and parallel to the interconnection line.

"In some embodiments, the interconnection line may be provided as a plurality of interconnection lines. Each of the interconnection lines may be connected to a pair of the first doped regions disposed at both sides thereof, and each of the first doped regions may be solely connected to the corresponding one of the interconnection lines.

"In some embodiments, the device may further include connecting portions interposed between the active patterns, with each of the connecting portions connecting the channel regions of the active patterns, arranged along a direction crossing the interconnection line.

"In some embodiments, the device may further include a buried dielectric interposed between the substrate and the active patterns.

"In some embodiments, the common source region may be connected to the variable resistance pattern.

"According to other example embodiments of inventive concepts, a semiconductor memory device may include active patterns arranged two-dimensionally on a substrate, with each of the active patterns including a first doped region and a second doped region, which may be spaced apart from each other in a direction normal to a top surface of the substrate. A channel region may be interposed between the first and second doped regions, and a common source region may be interposed between the substrate and the active patterns. Each of a plurality of gate patterns may be disposed to face a sidewall of the corresponding one of the active patterns. Each of a plurality of word lines may be connected in common to the gate patterns arranged along a direction, on the substrate. Each of a plurality of variable resistance patterns may be connected to the second doped region of the corresponding one of the active patterns. Interconnection lines may be disposed to cross the word lines. Each of the interconnection lines may be connected to the variable resistance patterns arranged parallel to the word lines, and may connect portions disposed between the active patterns arranged parallel to the word lines.

"In some embodiments, each of the connecting portions may connect the channel regions of the active patterns, which may be arranged parallel to the word lines.

"In some embodiments, the device may further include gate dielectrics, each of which may be interposed between the corresponding one of the active patterns and the corresponding one of the gate patterns.

"In some embodiments, the device may further include a gap-fill dielectric interposed between the substrate and the common source region.

"In some embodiments, the common source region connects the first doped regions of the active patterns with each other."

For the URL and additional information on this patent, see: Kim, Sua; Kim, Jin Ho; Park, Chulwoo; Lee, Sangbo; Hwang, Hongsun. Semiconductor Memory Devices Including Vertical Transistor Structures. U.S. Patent Number 8809926, filed September 6, 2012, and published online on August 19, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8809926.PN.&OS=PN/8809926RS=PN/8809926

Keywords for this news article include: Semiconductor, Random Access Memory, Samsung Electronics Co. Ltd..

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Source: Electronics Newsweekly


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