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Patent Issued for Semiconductor Memory Device, Method of Fabricating the Same, and Devices Employing the Semiconductor Memory Device

September 3, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- Samsung Electronics Co., Ltd. (KR) has been issued patent number 8809932, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventors are Cho, Byung-Kyu (Seoul, KR); Lee, Se-Hoon (Yongin-si, KR); Park, Kyu-Charn (Pyeongtaek-si, KR); Lee, Choong-Ho (Seongnam-si, KR).

This patent was filed on July 6, 2007 and was published online on August 19, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "The present invention relates to a semiconductor memory device, a method of fabricating the same, and devices employing the semiconductor memory device.

"Non-volatile memory devices retain stored information even when not powered. One example of a non-volatile memory device is a flash memory. Many non-volatile memories have a memory cell array structure where the memory cells are floating gate transistors. Generally, these memory cells include a floating gate disposed between a semiconductor substrate and a control gate. A tunnel insulation layer often separates the floating gate from the semiconductor substrate. A drain and source are generally disposed on either side of the floating gate in the semiconductor substrate. During operation, charges are injected into or pulled from the floating gate by application of voltages to the control gate, drain and/or source.

"A potential Vfg of the floating gate when a write potential Vcg is applied to the control gate is determined by capacitive coupling as represented by equations 1 and 2 below: Vfg=Cr(Vcg-Vt-Vt0) (1) Cr=Cip/(Cip+Ctun) (2) where Vt is the present cell transistor threshold value, Vt0 is the threshold value (neutral threshold value) when no electric charge is stored in the floating gate, and Cr is the capacitive coupling ratio of the memory cell. As shown by equation 2, the capacitive coupling ratio Cr depends on i) the capacitance Cip between the control gate and the floating gate and ii) the capacitance Ctun between the floating gate and the semiconductor substrate.

"As Vfg rises, an electric field acting on the tunnel insulation layer increases, and this facilitates injection of electric charge into the floating gate. In addition, according to the above equations, when Vcg is constant, Vfg increases in proportion to a capacitance ratio Cr. That is, when this capacitance ratio Cr is large, a Vfg large enough to move electric charge can be obtained even if the write potential Vcg is decreased. As a consequence, the write potential can be reduced."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "The present invention relates to a semiconductor memory device.

"In one embodiment, the semiconductor memory device includes a semiconductor substrate having projecting portions, a tunnel insulation layer formed over at least one of the projecting semiconductor substrate portions, and a floating gate structure disposed over the tunnel insulation layer. An upper portion of the floating gate structure is wider than a lower portion of the floating gate structure, and the lower portion of the floating gate structure has a width less than a width of the tunnel insulating layer. First insulation layer portions are formed in the semiconductor substrate and project from the semiconductor substrate such that the floating gate structure is disposed between the projecting first insulation layer portions. A dielectric layer is formed over the first insulation layer portions and the floating gate structure, and a control gate is formed over the dielectric layer.

"Another embodiment of the semiconductor memory device includes a semiconductor substrate, and a floating gate structure disposed over the substrate. An upper portion of the floating gate structure is wider than a lower portion of the floating gate structure. First insulation layer portions are formed in the semiconductor substrate and project from the semiconductor substrate such that the floating gate structure is disposed between the projecting first insulation layer portions, and an upper surface of the floating gate structure is below an upper surface of the projecting first insulation layer portions. A dielectric layer is formed over the first insulation layer portions and the floating gate structure. A control gate is formed over the dielectric layer.

"A further embodiment of the semiconductor memory device includes a semiconductor substrate, and a floating gate structure disposed over the substrate. An upper portion of the floating gate structure is wider than a lower portion of the floating gate structure. First insulation layer portions are formed in the semiconductor substrate and project from the semiconductor substrate such that the floating gate is disposed between the projecting first insulation layer portions. The projecting first insulation layer portions define a recess exposing an upper portion of the floating gate structure. A dielectric layer is formed over the first insulation layer portions and the floating gate structure such that the dielectric layer is formed in at least a portion of the recess. A control gate is formed over the dielectric layer.

"The present invention also relates to a method of forming a semiconductor memory device.

"In one embodiment, the method includes forming a floating gate structure on a semiconductor substrate using a mask pattern, and etching a lower portion of the floating gate structure such that the lower portion of the floating gate structure is less wide than an upper portion of the floating gate structure. In this embodiment, the method further includes forming a first insulation layer over the semiconductor substrate, etching the first insulation layer to expose the mask pattern, etching the mask pattern to create a recess defined by the first insulation layer that exposes the floating gate structure, forming a dielectric layer over the first insulation layer such that the dielectric layer is formed in at least a portion of the recess, and forming a control gate over the dielectric layer.

"In another embodiment, the method includes forming a first floating gate over a semiconductor substrate using a mask pattern, forming a first insulation layer over the semiconductor substrate, etching the first insulation layer to expose the mask pattern, etching the mask pattern to create a first recess defined by the first insulation layer that exposes the first floating gate, and forming a second floating gate layer over the semiconductor substrate such that the second floating gate layer fills at least a portion of the first recess. In this embodiment, the method further includes etching the second floating gate layer to form a second floating gate such that a second recess is defined by the first insulation layer that exposes the second floating gate. A dielectric layer is formed over the first insulation layer such that the dielectric layer is formed in at least a portion of the second recess, and a control gate is formed over the dielectric layer.

"The present invention still further relates to a memory device that includes a memory array having an array of memory cells, and each memory cell is configured according to one of the above described embodiments. Control circuitry is configured to read data from and write data to the memory array.

"The present invention also relates to a memory system including a memory device and a memory controller. The memory controller is configured to control the memory device.

"The memory device includes an array of memory cells, and each memory cell is configured according to one of the above described embodiments.

"The present invention further relates to a processing system.

"In one embodiment, the processing system includes a central processing unit and a memory device operatively connected to the central processing system. The memory device includes a memory array having an array of memory cells, and each memory cell is configured according to one of the above described embodiments."

For the URL and additional information on this patent, see: Cho, Byung-Kyu; Lee, Se-Hoon; Park, Kyu-Charn; Lee, Choong-Ho. Semiconductor Memory Device, Method of Fabricating the Same, and Devices Employing the Semiconductor Memory Device. U.S. Patent Number 8809932, filed July 6, 2007, and published online on August 19, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8809932.PN.&OS=PN/8809932RS=PN/8809932

Keywords for this news article include: Semiconductor, Capacitive Coupling, Samsung Electronics Co. Ltd..

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Source: Electronics Newsweekly


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