News Column

Patent Issued for Semiconductor Device, Substrate and Semiconductor Device Manufacturing Method

September 3, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Kasuya, Yasumasa (Kyoto, JP); Haga, Motoharu (Kyoto, JP); Matsubara, Hiroaki (Kyoto, JP), filed on February 28, 2011, was published online on August 19, 2014.

The assignee for this patent, patent number 8810016, is Rohm Co., Ltd. (Kyoto, JP).

Reporters obtained the following quote from the background information supplied by the inventors: "As a surface mounting type package, BGA (Ball Grid Array) is typically known.

"FIG. 9 is an illustrative sectional view showing a configuration of a semiconductor device which adopts the BGA. The semiconductor device includes a semiconductor chip 101, an interposer 102 equipped with the semiconductor chip 101, and a sealing resin 103. The sealing resin 103 seals the semiconductor chip 101 as well as a surface that opposes to the semiconductor chip 101 on the interposer 102.

"The interposer 102 has a resin substrate 104 formed of an insulative resin as a base substrate and includes an island 105 and a plurality of internal terminals 106 on one side of the resin substrate 104. The island 105 is formed in a generally rectangular shape with a size greater than the semiconductor chip 101 as seen from top. The island 105 is bonded to the back surface of the semiconductor chip 101 with a bonding material 107. A plurality of internal terminals 106 are disposed around the island 105 and electrically connected by a bonding wire 108 to the electrode pad (not shown) on the front surface of the semiconductor chip 101 that is bonded to the island 105. On the other surface of the resin substrate 104, a plurality of ball shaped external terminals 109 are disposed in an aligned manner for electrically connected to a land on the mounting substrate (printed wiring board). The internal terminals 106 on one surface of the resin substrate 104 and the external terminals 109 on the other surface of the resin substrate 104 are electrically connected via a metal provided within a through hole (not shown) that extends from one surface to the other surface of the resin substrate 104.

"In such semiconductor devices, an epoxy resin bonding adhesive, a silver paste, or an insulating paste is typically used as the bonding material 107 for bonding the semiconductor chip 101 to the island 105. Bonding materials using a soldering material have not been provided at present for this purpose.

"For example, a semiconductor chip built with a power IC operates with the back surface (the back surface of a semiconductor substrate) serving as a ground. For this reason, in the case where a semiconductor chip built with the power IC is provided as the semiconductor chip 101 shown in FIG. 9, the islands 105 and the external terminals 109 are electrically connected, and at the same time, the back surface of the semiconductor chip 101 must be bonded to the islands 105 with an electrically conductive bonding material 107. However, in the case where the soldering material is employed as the bonding material 107, when the temperature of the semiconductor device changes rapidly or drops after the bonding under high temperatures, the peripheral portion on the back surface side of the semiconductor chip 101 may be applied with a stress from the bonding material 107 and this may cause damages such as crack at the peripheral portion. When the soldering material is employed as the bonding material 107, for example, a reflow soldering is absolutely required. During the cooling process after the reflow soldering, a difference in heat shrinkage amount is generated between the interposer 102 (resin substrate 104) and the semiconductor chip 101 and causes a stress. The stress caused by the difference in heat shrinkage amount is then transferred from the bonding material 107 to the peripheral portion on the back surface of the semiconductor chip 101.

"Such problem also occurs in the case where a semiconductor chip is bonded with a soldering material to a dye pad of a lead frame having a relatively small thickness.

"On the other hand, methods of die bonding a semiconductor chip include a method including the steps of forming a lead frame or a plating layer such as silver, palladium, and gold on the surface of the organic substrate or the like, applying solder thereto, using the applied solder as a bonding material, and then pressing and mounting a semiconductor chip to the bonding material.

"Along with recent development of a highly integrated semiconductor chip, the advancement of a wire bonding technology has achieved a bonding pad having a smaller and finer pitch, and as a result, the number of wire bonding that is able to be connected in a semiconductor chip having an identical size, in other words, the number of the bonding wires required for wiring a single semiconductor chip, is in the increase.

"Accordingly, this tends to cause various problems including: failures in wire bonding due to misalignment of a semiconductor chip, failures such as edge touch and short circuit due to the nonuniform loop-like shape of the bonding wire after the wire bonding process, or failures due to a narrow space between bonding wires. Consequently, a precise mounting positioning is required when mounting the semiconductor chip.

"In order to solve these problems, the alignment process has been conventionally performed in such a way that two components to be aligned with each other are provided with a portion having a greater wettability and a portion having a less wettability, and the portion with greater wettability is applied with a liquid such as a bonding adhesive and is overlapped with the other component to change the relative position of the two components by way of the surface tension of the liquid (see Patent Document 2, for example).

"With referring to FIGS. 10(a) and 10(b) and FIGS. 11(a) through 11(d), the case in which the alignment method disclosed in Patent Document 2 is adopted as the die bonding process of the semiconductor chip will be described hereinafter.

"FIG. 10(a) is a plan view schematically showing an example of an island used in the conventional die bonding process, and FIG. 10(b) is a longitudinal sectional view schematically showing the island.

"As shown in FIGS. 10(a) and 10(b), on a part of the surface of an island 81, a solder-resist is applied and a solder-resist layer 84 is formed. A metal surface 83 is not applied with the solder-resist and the island 81 is exposed thereon, whereby the metal surface 83 is easily wet by solder. On the other hand, on the solder-resist layer 84 the solder is difficult to wet. The metal surface 83 has a square shape, which is identical with the shape of the back surface of the semiconductor chip which is subject to subsequent die bonding process.

"FIGS. 11(a) through FIG. 11(d) are a flow chart schematically showing an example of conventional die bonding processes.

"First, a solder 86 is applied on the metal surface 83 on the island 81 by using a metal mask as shown in FIG. 11(a). Then, a semiconductor chip 82 is pressed against the solder 86 for fixing the semiconductor chip 82 as shown in FIG. 11(b). Next, the solder 86 is heated to melt as shown in FIG. 11©. The resultant molten solder 86a spreads over the entire bottom surface of the semiconductor chip 82 and then the semiconductor chip 82 moves under the influence of a surface tension toward a direction in which the metal surface 83 and the semiconductor chip 82 are opposed to each other, as shown in FIG. 11©. With this movement, the metal surface 83 of the island 81 and the semiconductor chip 82 are opposed to each other as shown in FIG. 11(d), and the alignment is complete.

"In accordance with the process mentioned above, the formation of the solder-resist layer 84 on a particular portion of the island 81 can provide two separate portions: one portion where the solder 86 does not wet (solder-resist layer 84) and the other portion where the solder 86 easily wets (metal surface 83). Under the influence of surface tension which acts to minimize the surface area of the droplet, the molten solder 86a pull the semiconductor chip 82 onto the metal surface 83 which is a target mounting position of the semiconductor chip 82. The metal surface 83 on the island 81 and the semiconductor chip 82 are thus opposed with each other to perform the alignment.

"However, as the semiconductor chip 82 moves in a manner to oppose to the metal surface 83 under the influence of surface tension of the molten solder 86a, the difference between the surface area of the molten solder 86a that is on the move and the surface area of the molten solder 86a that is in an opposed state gradually becomes smaller. Accordingly, the force to attract the semiconductor chip 82 by the action of surface tension gradually becomes weaker. Accordingly, due to the resistance force and the like that are caused by the viscosity of the solder, there exists some cases where it is impossible for the semiconductor chip 82 to move to a predetermined target position, and also there exists a problem that the semiconductor chip 82 cannot move precisely to a target position on the island 81. Patent Document 1: Japanese Unexamined Patent Publication No. 2001-181563 Patent Document 2: Japanese Unexamined Patent Publication No. 2001-087953"

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "Problems to be Solved

"It is an object of the present invention to provide a semiconductor device which can prevent damages in the semiconductor chip even with the use of a soldering material for bonding the back surface of the semiconductor chip to the bonding surface of chip junction portion such as an island or a dye pad.

"It is another object of the present invention to provide a semiconductor device, substrate, and methods for manufacturing the same, which allows precise die bonding of the semiconductor chip on the island.

"Solution to the Problems

"The semiconductor device according to one aspect of the present invention includes a semiconductor chip and a chip junction portion having a junction plane being bonded to the back surface of the semiconductor chip with a bonding material, wherein the area of the junction plane is made smaller than the area of the back surface of the semiconductor chip.

"According to this configuration, since the area of the junction plane of the chip junction portion is smaller in size than the area of the back surface of the semiconductor chip, when, for example, a soldering material (creamy solder) is applied on the junction plane of the chip junction portion and a semiconductor chip is disposed on the soldering material, the soldering material will not slip off the side surface of the semiconductor chip. Consequently, even in the case where a difference in the heat shrinkage level is caused between the semiconductor chip and the chip junction portion when the temperature of the semiconductor device changes rapidly or drops after the junction process under high temperatures, the configuration can prevent the application of the stress on the peripheral portion of the back surface of the semiconductor chip and can thus prevent damages on the semiconductor chip.

"It is preferable that the soldering material is one in which several types of soldering powders, different in grain size and melting point (composition), are mixed in a flux. Since in such a soldering material density of the soldering powders in the flux is high, the generation of voids therein can be prevented at the time of reflow melting process. Even when voids are generated, since the melting points of the soldering powders are different, the generated voids can be pushed out of the soldering material. The back surface of the semiconductor chip and the junction plane of the chip junction portion can thus be favorably bonded therebetween.

"Additionally, it is preferable that the semiconductor device further includes a plurality of extending portions that extend from the periphery of the junction plane in directions parallel to the junction plane. With this configuration, a soldering material is applied on the junction plane of the chip junction portion and a semiconductor chip is disposed on the soldering material to perform reflow soldering. Then, the soldering material is melt and the resulting melted liquid flows to move the semiconductor chip on the chip junction portion. Since the plurality of extending portions are provided, even when the semiconductor chip is disposed accidentally in a position displaced to a certain side of the extending portion, the melted liquid of the soldering material flows more into other extending portions. The flow of the melted liquid can lead the semiconductor chip at the center on the junction plane. For this reason, the semiconductor chip can be disposed on the junction plane with a greater tolerance, improving the productivity of the semiconductor device.

"As seen from top of the surface of the semiconductor chip to perpendicularly downward, the tip of the extending portion may reach the outside of the periphery of the semiconductor chip in a state where the semiconductor chip is bonded to the junction plane.

"Further, it is preferable that the junction plane is formed in a rectangular shape and that the extending portion extends from a corner of the junction plane.

"Moreover, it is more preferable that the extending portion extends from each of the four corners of the junction plane.

"The semiconductor device according to another aspect of the present invention includes a semiconductor chip, an island to which the semiconductor chip is die-bonded with a die bonding material, and a coating layer formed on a part of the surface of the island and formed of the die bonding material which is difficult to wet than the island. The exposed portion of the island which forms no coating layer includes a die bonding portion which is opposed to the back surface of the semiconductor chip and has a size smaller than the back surface of the semiconductor chip, and an alignment portion extending from the die bonding portion such that it includes a position that is opposed to the corner of the back surface of the semiconductor chip in the island.

"According to this configuration, the exposed portion of the island that forms no coating layer includes the die bonding portion which is opposed to the back surface of the semiconductor chip and has a size smaller than the back surface of the semiconductor chip, and the alignment portion extending from the die bonding portion such that it includes a position that is opposed to the corners of the back surface of the semiconductor chip in the island. The corners of the semiconductor chip are positioned on the alignment portion. Since the corners of the semiconductor chip are positioned on the alignment portion, and the die bonding is precisely performed, the nonuniform formation of the shape (loop shape) of the bonding wire can be prevented and the space between the bonding wires can also be prevented from becoming narrower.

"It is preferable that the die bonding material is a solder. In this case, it is preferable that the coating layer is formed of a material that the solder does not wet. This configuration uses a solder with a relatively low viscosity at the time of melting. Accordingly, in the alignment process in which the semiconductor chip is aligned at the time of the die bonding, the solder is melted to precisely move the corners of the semiconductor chip to desired target positions on the alignment portion to achieve a precise alignment. As a result, the semiconductor chip is more precisely die-bonded and thus ensures to prevent the nonuniform formation of the shape (loop shape) of the bonding wire and can also prevent the space between the bonding wires from becoming narrow.

"The substrate according to the present invention includes an island that is die-bonded to the semiconductor chip with a die bonding material, and a coating layer formed on a part of the surface of the island and formed of a die bonding material which is difficult to wet more than the island. The exposed portion of the island which forms no coating layer includes a die bonding portion which is opposed to the back surface of the semiconductor chip and has a size smaller than the back surface of the semiconductor chip, and an alignment portion extending from the die bonding portion such that it includes positions that are opposed to the corners of the back surface of the semiconductor chip on the island.

"According to this configuration, the exposed portion that forms no coating layer of the island includes a die bonding portion which is opposed to the back surface of the semiconductor chip to be die-bonded and has a size smaller than the back surface of the semiconductor chip, and an alignment portion extending from the die bonding portion such that it includes positions that are opposed to the corners of the back surface of the semiconductor chip in the island. Accordingly, in the alignment process in which the semiconductor chip is aligned at the time of die bonding, the solder is melted to attract the corners of the semiconductor chip to the alignment portion. In such manner, the surface tension which moves the semiconductor chip to the target position acts effectively for a precise alignment of the semiconductor chip. Consequently, use of this substrate in the manufacture of semiconductor device can avoid failures caused by a misalignment of the semiconductor device.

"By way of forming the coating layer in which the bonding material is difficult to wet more than the island, the portion on which no coating layer is formed, that is, the portion of greater wettability (exposed portion), can be formed in a particular shape. In this manner, the exposed portion is formed in order to allow the surface tension which moves the semiconductor chip to a target position to act effectively in accordance with a shape of the semiconductor chip to be die-bonded. Accordingly, in the present invention, semiconductor devices which have different shapes of semiconductor chips can be manufactured using a common substrate only by changing a shape of an exposed portion formed on the island.

"It is preferable that the die bonding material is a solder. In this case, it is preferable that the coating layer is formed of a material which does not wet the solder. According to this configuration, a solder with a relatively low viscosity at the time of melting will be used. Accordingly, in the alignment process in which the semiconductor chip is aligned at the time of the die bonding, the solder is melted to precisely move the corners of the semiconductor chip to desired target positions on the alignment portion to achieve a precise alignment. As a result, more precise die bonding can be achieved and the use of this substrate for manufacture of the semiconductor device can avoid failures of the semiconductor device caused by the misalignment of semiconductor chip.

"The method for manufacturing the semiconductor device according to the present invention includes a step for preparing an island. On a part of the surface of the island is formed with a coating layer of which die bonding material is difficult to wet more than the island. The exposed portion that forms no coating layer includes a die bonding portion which has a size smaller than the back surface of the semiconductor chip, and an alignment portion extending from the die bonding portion such that it includes positions to be opposed to the corners of the back surface of the semiconductor chip. The manufacturing method further includes the steps of: coating the die bonding material on the exposed portion; having the back surface of the semiconductor chip opposed to the die bonding portion and mounting the semiconductor chip on the island that is applied with the die bonding material in the previous coating process; and aligning the position of the semiconductor chip by melting the die bonding material for moving the corners of the semiconductor chip on the alignment portion.

"According to this process, the exposed portion of the island that forms no coating layer includes a die bonding portion which is opposed to the back surface of the semiconductor chip to be die-bonded and has a size smaller than the back surface of the semiconductor chip, and an alignment portion extending from the die bonding portion such that it includes positions that are opposed to the corners of the back surface of the semiconductor chip. Accordingly, after mounting the semiconductor chip on the island, in the alignment process, the die bonding material is melted to attract the corners of the semiconductor chip onto the alignment portion. In such manner, the surface tension which moves the semiconductor chip to a target position acts effectively for a precise alignment of the semiconductor chip and can thus avoid failures of the semiconductor device caused by the misalignment of semiconductor chip.

"It is preferable that the process for preparing the island includes a coating layer forming process for forming the coating layer by coating a material which is difficult to wet more than the island on the surface of the island except for a region corresponding to the exposed portion. In other words, the die bonding portion and the alignment portion are formed by coating the material of which die bonding material is difficult to wet in order to render the surface tension which moves the semiconductor chip to a target position to act effectively in accordance with the shape of the back surface of the semiconductor chip to be die-bonded. In this manner, even in the case of manufacturing several types of semiconductor devices which have different shapes of semiconductor chips to be die-bonded, the die bonding portion and the alignment portion to be formed may simply change their shape in accordance with the shapes of the semiconductor chip to be die-bonded. In this way, different shapes of semiconductor devices can be easily manufactured using a common substrate.

"It is preferable that the die bonding material is a solder. In this case, it is preferable that the coating layer is formed of a material which does not wet the solder. According to this method, a solder with a relatively low viscosity at the time of melting is used for die-bonding. Accordingly, the solder is melted to precisely move the corners of the semiconductor chip to desired target positions on the alignment portion. As a result, more precise die bonding can be achieved and can thus avoid failures of semiconductor device due to the misalignment of the semiconductor chip.

"These and other objects, features and effects of the present invention will become apparent from the description of the following embodiments with reference to the attached drawings."

For more information, see this patent: Kasuya, Yasumasa; Haga, Motoharu; Matsubara, Hiroaki. Semiconductor Device, Substrate and Semiconductor Device Manufacturing Method. U.S. Patent Number 8810016, filed February 28, 2011, and published online on August 19, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8810016.PN.&OS=PN/8810016RS=PN/8810016

Keywords for this news article include: Electronics, Rohm Co. Ltd., Semiconductor.

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Source: Electronics Newsweekly


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