News Column

Patent Issued for Seal Ring Structure with Capacitor

September 3, 2014

By a News Reporter-Staff News Editor at Electronics Newsweekly -- Mediatek Inc. (Hsin-Chu, TW) has been issued patent number 8810001, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventors are Hung, Cheng-Chou (Hukou Township, Hsinchu County, TW); Lee, Tung-Hsing (Lujhou, TW); Huang, Yu-Hua (Hsinchu, TW); Yang, Ming-Tzong (Baoshan Township, Hsinchu County, TW).

This patent was filed on January 16, 2012 and was published online on August 19, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "The invention relates to a semiconductor device and more particularly to a seal ring structure with a capacitor.

"In the manufacturing of integrated circuits (ICs), seal ring (also called as a guard ring) formation is an important part for semiconductor processes. A semiconductor device such as an IC is manufactured in a form of a chip cut out from a semiconductor wafer having an IC pattern formed thereon. A plurality of chips are formed by dicing the semiconductor wafer. In the dicing process, semiconductor chips are separated from each other, and mechanical stress such as vibration is usually applied to the semiconductor substrate/wafer. Accordingly, a crack on the chip may be caused when the dicing process is performed.

"Moreover, a plurality of semiconductor elements are formed on the semiconductor substrate. At this time, stacked insulating films, such as intermetal dielectric (IMD) films and/or interlayer dielectric (ILD) films, deposited during formation of the semiconductor elements are exposed from the cut section of the dicing line portions. These stacked insulating films and interfaces therebetween create paths for moisture to penetrate, and may cause a malfunction of the semiconductor device.

"In order to prevent semiconductor chips from damage caused by the dicing process and from moisture-induced degradation, a seal ring structure is provided between an IC pattern region and a dicing line of each chip. A conventional seal ring structure is formed in the process for forming wiring layers and contact portions and is a multi-layer structure composed of alternating metal and insulating layers. Vias are formed in each of the insulating layers to provide electrical paths between adjacent metal layers. However, the lowermost metal layer in the seal structure electrically contacts with the semiconductor substrate and thus creates a substrate short-circuit path around the semiconductor chip. The seal ring structure provides a very low resistance metal path around the periphery of the semiconductor chip, such that noise can travel from the IC region of the semiconductor chip to the seal ring structure, resulting in the substrate noise coupling issue.

"Accordingly, there is a need to develop a novel seal ring structure which is capable of mitigating or eliminating the aforementioned problem."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "An exemplary embodiment of a semiconductor device comprises a semiconductor substrate of a conductivity type having a chip region enclosed by a seal ring region. An insulating layer is on the semiconductor substrate. A seal ring structure is embedded in the insulating layer corresponding to the seal ring region. A capacitor is disposed under the seal ring structure and is electrically connected thereto, wherein the capacitor comprises a body of the semiconductor substrate."

For the URL and additional information on this patent, see: Hung, Cheng-Chou; Lee, Tung-Hsing; Huang, Yu-Hua; Yang, Ming-Tzong. Seal Ring Structure with Capacitor. U.S. Patent Number 8810001, filed January 16, 2012, and published online on August 19, 2014. Patent URL:

Keywords for this news article include: Electronics, Mediatek Inc., Semiconductor.

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Source: Electronics Newsweekly

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