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Patent Issued for Partially Depleted (PD) Semiconductor-On-Insulator (SOI) Field Effect Transistor (FET) Structure with a Gate-To-Body Tunnel Current...

September 3, 2014



Patent Issued for Partially Depleted (PD) Semiconductor-On-Insulator (SOI) Field Effect Transistor (FET) Structure with a Gate-To-Body Tunnel Current Region for Threshold Voltage (Vt) Lowering and Met

By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent by the inventors Anderson, Brent A. (Jericho, VT); Bryant, Andres (Burlington, VT); Liang, Jiale (Stanford, CA); Nowak, Edward J. (Essex Junction, VT), filed on January 3, 2014, was published online on August 19, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8809954 is assigned to International Business Machines Corporation (Armonk, NY).

The following quote was obtained by the news editors from the background information supplied by the inventors: "The present invention relates to partially depleted (PD) semiconductor-on-insulator (SOI) field effect transistors (FETs) and, more specifically, to embodiments of a PDSOIFET structure with a gate-to-body tunnel current region for threshold voltage (Vt) lowering and a method of forming the PDSOI FET structure.

"A semiconductor-on-insulator (SOI) field effect transistor (FET) is a FET formed in the semiconductor layer of a semiconductor-on-insulator (SOI) wafer. Shallow trench isolations (STI) structures extend through the semiconductor layer and isolate the SOI FET from other devices within the semiconductor layer. As with any FET, an SOIFET comprises a channel region positioned between source/drain regions and a gate structure positioned above the channel region. However, depending upon the configuration of the source/drain regions as well as the thickness of the semiconductor layer, the channel region of the SOIFET may be fully depleted (FD) or partially depleted (PD). Specifically, in a FDSOIFET, the depletion layer of the channel region between the source/drain regions encompasses the full thickness of the semiconductor layer. In a PDSOIFET, the depletion layer between the source/drain regions is only located in an upper portion of the semiconductor layer near the top surface.

"In a PDSOIFET, the non-depleted portion of the channel region that is between the source/drain regions and below the depletion layer is typically referred to as the body of the FET. If this body is not contacted, it is referred to as a floating body. Since the floating body is not contacted (i.e., not biased), its voltage may vary (e.g., as result of leakage currents to Vdd or ground). Variations in the voltage of the floating body will lead to variations in the threshold voltage (Vt) of the PDSOIFET. Furthermore, such threshold voltage variations can differ between PDSOIFETs at different locations within an electronic circuit and can, thereby degrade the performance of the electronic circuit. Performance degradation is particularly notable when some FETs within the electronic circuit require lower threshold voltages than others. For example, in a static random access memory (SRAM) cell within an SRAM array, the pull-down FETs require a lower threshold voltage than the pull-up and pass-gate FETs. Therefore, there is a need in the art for a floating body PDSOIFET structure that provides for threshold voltage (Vt) lowering to, for example, ensure that a FET requiring a lower threshold voltage than other FETs in the same electronic circuit will have a lower threshold voltage."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "In view of the foregoing, disclosed herein are embodiments of a floating body partially depleted semiconductor-on-insulator field effect transistor (PDSOIFET) structure having a gate-to-body tunnel current region that provides for threshold voltage (Vt) lowering without increasing gate current or other leakage currents. In one embodiment, a semiconductor layer has a center portion with a first conductivity type. A gate structure traverses the center portion. This gate structure has adjacent sections with different conductivity types in order to create, within the center portion of the semiconductor layer, a channel region below one section and a gate-to-body tunnel current region below another section. In another embodiment, a semiconductor layer has a center portion with a channel region and a gate-to-body tunnel current region adjacent to the channel region. The channel region is doped with a dopant having a first conductivity type. The gate-to-body tunnel current region comprises: a first implant region immediately adjacent to the channel region and doped with a higher concentration of the same dopant; a second implant region adjacent to the first implant region and having a second conductivity type; and an enhanced generation and recombination region between the first and second implant regions. A gate structure with the second conductivity type traverses the center portion. The PDSOIFET structure embodiments can, for example, be incorporated into any electronic circuit with some FETs requiring a lower threshold voltage than others (e.g., in an Static Random Access Memory (SRAM) array, where pull-down FETs require a lower threshold voltage that pass-gate or pull-up FETs). Also disclosed herein are embodiments of methods of forming these structures

"More particularly, one embodiment of a field effect transistor, according to the present invention, can comprise a semiconductor layer having end portions and a center portion between the end portions. The center portion can comprise a channel region and a gate-to-body tunnel current region positioned laterally adjacent to the channel region. The channel region and gate-to-body tunnel current region can each have a first conductivity type. A gate structure can traverse the center portion of the semiconductor layer and, specifically, both the channel region and the gate-to-body tunnel current region. This gate structure can comprise a gate dielectric layer on the top surface of the semiconductor layer and a gate conductor layer on the gate dielectric layer. The gate conductor layer can specifically comprise a first conductive section and a second conductive section positioned laterally adjacent to and different from the first conductive section. Specifically, the first conductive section can be positioned on the gate dielectric layer aligned above the gate-to-body tunnel current region and can have the first conductivity type. The second conductive section can be positioned on the gate dielectric layer aligned above the channel region and can have a second conductivity type different from the first conductivity type.

"An embodiment of a method of forming this field effect transistor structure can comprise providing a semiconductor layer having end portions and a center portion between the end portions. A gate structure can be formed such that it traverses the center portion. Specifically, a gate dielectric layer can be formed on the top surface of the semiconductor layer. Then, a gate conductor layer can be formed on the gate dielectric layer such that the gate conductor layer comprises: a first conductive section and a second conductive section positioned laterally adjacent to the first conductive section. The first conductive section can be formed such that it has a first conductivity type and such that it is aligned above a first conductivity type gate-to-body tunnel current region within the center portion of the semiconductor layer. The second conductive section can be formed such that it has a second conductivity type different from the first conductivity type and such that it is aligned above a first conductivity type channel region within the center portion of the semiconductor layer. Once the gate structure is formed, additional conventional processing can be performed to complete the field effect transistor structure.

"Another embodiment of a field effect transistor structure, according to the present invention, can comprise a semiconductor layer having end portions and a center portion between the end portions. The center portion can further have an area that extends laterally beyond the end portions and can comprise a channel region and a gate-to-body tunnel current region positioned laterally adjacent to the channel region. Specifically, the channel region can be positioned between the end portions and can be doped with a first conductivity type dopant such that it has a first conductivity type. The gate-to-body tunnel current region can be adjacent to the channel region in the area of the center portion that extends laterally beyond the end portions. This gate-to-body tunnel current region can comprise a first implant region that is immediately adjacent to the channel region and doped with the first conductivity type dopant at a higher concentration than the channel region. The gate-to-body tunnel current region can further comprise a second implant region adjacent to the first implant region and doped with a second conductivity type dopant different from the first conductivity type dopant such that the second implant region has a second conductivity type. Finally, the gate-to-body tunnel current region can comprise an enhanced generation and recombination region at the junction between the first implant region and the second implant region. A gate structure can traverse the center portion and, specifically, can traverse both the gate-to-body tunnel current region and the channel region.

"An embodiment of a method of forming this field effect transistor structure can comprise providing a semiconductor layer doped with a first conductivity type dopant such that the semiconductor layer has the first conductivity type. This semiconductor layer can further have end portions and a center portion between the end portions, the center portion can have an area that extends laterally beyond the end portions. Next, a gate-to-body tunnel current region can be formed in the area of the center portion that extends laterally beyond the end portions. Specifically, a first implant region can be formed within this area and immediately adjacent to a designated channel region that is in the center portion between the end portions. This first implant region can be formed such that it is doped with the first conductivity type dopant at a higher concentration than the channel region. Additionally, a second implant region can be formed adjacent to the first implant region. This second implant region can be formed such that it is doped with a second conductivity type dopant different from the first conductivity type dopant such that the second implant region has a second conductivity type different from the first conductivity type. Finally, an enhanced generation and recombination region can be formed at the junction between the first implant region and the second implant region. Once the gate-to-body tunnel current region is formed, a gate structure can be formed such that it traverses the center portion, including the gate-to-body tunnel current region and channel region, and additional conventional processing can be performed to complete the field effect transistor structure."

URL and more information on this patent, see: Anderson, Brent A.; Bryant, Andres; Liang, Jiale; Nowak, Edward J.. Partially Depleted (PD) Semiconductor-On-Insulator (SOI) Field Effect Transistor (FET) Structure with a Gate-To-Body Tunnel Current Region for Threshold Voltage (Vt) Lowering and Method of Forming the. U.S. Patent Number 8809954, filed January 3, 2014, and published online on August 19, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8809954.PN.&OS=PN/8809954RS=PN/8809954

Keywords for this news article include: Electronics, Semiconductor, Random Access Memory, International Business Machines Corporation.

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Source: Electronics Newsweekly


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