News Column

Patent Issued for Multiple Read Port Memory System with a Single Port Memory Cell

September 3, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- International Business Machines Corporation (Armonk, NY) has been issued patent number 8811102, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventors are Le, Thoai Thai (Cary, NC); Atwal, Jagreet S. (Cary, NC).

This patent was filed on January 16, 2013 and was published online on August 19, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "The present disclosure generally relates to microprocessors and microprocessor memory systems, and more specifically, an apparatus and method for providing multiple read port memory system with a single port memory cell.

"Microprocessors use memory arrays such as register files to store data temporarily for a processing unit. To enable simultaneous access to a memory cell array, register files are used to provide multiple read and/or write ports. Depending on application these so called multi-port register files can be configured up to eight or even more read ports.

"FIG. 2 illustrates a block diagram of a conventional (1 Write, 4 Read) 1W4R register file 10. While an address read architecture is depicted, it is understood that a write word line configuration (not shown) uses a similar architecture as known in the art. In the read word line implementation, the 1W4R register file 10 provides four read Address Decoder elements DCD.sub.0, . . . , DCD.sub.3 elements 15_0, . . . 15_3 respectively, for each of the four read ports 1W4R (1 Write, 4 Read) port bit cells 30_0, . . . , 30_3 respectively. Each respective decoder element 15_0, . . . 15_3 receives a respective read enable bit decoder selector signal and respective read address bits, (e.g., 2 bits) collectively at respective read address bit input lines 12_0, . . . 12_3. When enabled, the decoder element 15_0, . . . , 15_3 generates, in response to the 2 read address inputs, respective parallel output read address decode bits 17 on a bus. In the implementation shown, a 2:4 read address decoder element 15_0, . . . , 15_3 provides an output of four read address decode bits 17. As further shown in FIG. 2, a corresponding clock control buffer device 20_0, . . . , 20_3 is provided to receive the four read address output bits 17 of the respective enabled decoder element 15_0, . . . , 15_3. The inset of FIG. 2 shows a detailed processing at a clock control buffer element 20_3 where a received decoder parallel output bit 17 is combined using an AND or similar logic gate 23, with a read control clock signal 25 to clock in the four parallel read address decode signals, referred to as RWL.sub.0, . . . , RWL.sub.3 22 in a read operation. A respective set 22_0, . . . , 22_3 of Read Word Line (RWL.sub.0, . . . , RWL.sub.3) signals is input to a respective 1W4R port bit cell 30_0, . . . , 30_3 to selectively read the data value stored therein. Each Read Word Line signal 22 is received at a respective read port pass gate circuit to drive the corresponding output bit cell value (e.g., truth or its complement) at a corresponding local bit line 37. Read output data on the local bit line LBL.sub.0, . . . , LBL.sub.3 are output as register file 10 outputs RD0-RD3 via processing at respective local receiver element 40 and global receiver and output driver element 50.

"A write word line implementation for writing data to a register file is also provided using a similar structure. In the case of write operations (not shown), the same structures are implemented, i.e., a write enable bit, and write address bits (not shown) are input to a respective write decoder (not shown) where the outputs are gated, using a clock (CLK) control buffer and bit cell to generate write bits, e.g., Write Word Line (WWL) bits for performing a 1W4R bit cell write operation.

"Depending on an application, a multi-port register file can be configured up to eight or more read ports.

"FIG. 1 shows a detailed schematic diagram of a conventional 1W4R port bit cell circuit 30 (representing a single 1W4R circuit 30_0, . . . , 30_3 of FIG. 2). Each bit cell 30 includes one write port and four read ports and implements a single memory bit cell (single bit cell) 75 of a conventional 6-transistor memory bit cell design implementing a cross-coupled inverter configuration and includes a single read port.

"As shown in FIG. 1, to write data to single bit cell 75, input Write Word Line (WWL) 29 receives decoded write signal from write decode circuitry (not shown) to activate storing a data value at respective bit cell node 82 and complementary bit cell node 84 of the bit cell 75 in conjunction to data value inputs WBL0.sub.--t (e.g., write bit line 0 true data value) and WBL0.sub.--c (e.g., write bit line 0 complement data value). For example, a low or '0' value WWL signal may represent a bit cell hold operation, while a high or logic '1' value WWL signal may represent a bit cell write operation.

"In FIG. 1, at each local bit line LBL0, . . . , LBL3 corresponding to local bit lines 37.sub.0, . . . , 37.sub.3, there is connected a pass gate selection circuit 90 comprising a serial configuration of parallel operated pull-down NMOS FET devices N0, N1. Data values at LBL0, . . . LBL3 are read out under control of NMOS device N0 coupled to a respective read word line RWL.sub.0, . . . , RWL.sub.3 that each receive decoded address signals to drive the respective read bit lines 37.sub.0, . . . , 37.sub.3 to its true (or complementary) values based on the data written to and stored at the bit cell nodes 82 (84). For each read port, a data value stored at a single bit cell node 82 or 84 is read out by a corresponding NMOS transistor device N1 whose gate is connected to the corresponding cell node. In the example circuit 30 of FIG. 1, a local bit line data value corresponding to a true value is read from read bit lines LBL1.sub.--t and LBL3.sub.--t of 1W4R bit cell circuit, and its complement value is provided at complement read bit lines LBL0.sub.--c, LBL2c. Read bit lines LBL0, . . . LBL3 are usually pre-charged to high values, e.g., in a pre-charge phase using a local_prch signal 42 (i.e., local_prch=0) until the bit cell 75 drives the bitline high or low according to the stored bit cell data value in the evaluation phase of a read process (local_prch=1).

"Selection circuits (i.e., N0, N1 pass gates) can be added as many as read ports are needed. However, additional register file cell circuitry and wire lines are required taking up much more chip area.

"FIG. 3 depicts a further conventional circuit 125 for reading out data values from 1W4R port register file 30 of FIG. 1. This read process occurs in two stages via the local receiver circuits 40 and global receiver and output driver circuits 50. When selected, read data for each port is driven from the cell nodes to the local bitline (LBL0, . . . , LBL3) and fed to the corresponding local receiver 40_0, . . . , 40_3 which in turn drives the data on respective lines global bit lines GBL0, . . . , GBL3 through the global receiver 50 provide the read data output RD0-RD3 in parallel. As known in the art, each local receiver 40.sub.0, . . . , 40.sub.3 includes an inverter as amplifier, pull-up transistor devices (pre-charge and keeper) 45 and a, NMOS transistor device 46 in a pull-down configuration at the local receiver for driving the read local bitline data values on respective lines global bit lines GBL3.sub.0, . . . , GBL.sub.3 for receipt at the global receiver 50.

"One drawback of the conventional multi-port register file architecture 10 of FIG. 2, is that cell area and the wire pitch area increases typically linearly to the number of the read ports. While growing cell height is not an issue, increasing in width is in general strictly limited due to a predefined standard cell pitch.

"Furthermore, bit cell layout design is very challenging with increasing number of ports. Being located in a very congested area, it is very likely that a multi-port bitcell may exhibit more crosstalk coupling occurring between adjacent bitlines and word lines.

"Further, with the additional loading on each of the storage nodes (true/comp), read/write access times increases accordingly to the number of the ports.

"Furthermore, as there is one decoder for each read port, the decoded address is combined with the read clock in the clock control buffer to generate the read word lines. As indicated in FIG. 2 wiring becomes more and more complex in this particular region with increasing number of read ports.

"It would be highly desirable to provide a more area efficient register file with multiple read ports, and a method for operating the register file, that avoids the drawbacks of the conventional multi-port cell architecture."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "There is provided, in one aspect, a register file circuit with multiple read ports using a single port memory bit cell that avoids the drawbacks the conventional multi-port register file implementations.

"In one aspect, there is provided a register file with multiple read ports and method of operating. The register file with multiple read-ports comprises: n single memory bit cells where n is an integer equal to or greater than 2, each single memory bit cell storing a data value and providing a respective a single bit cell write port and a respective single read port connecting a respective local read bit line for transmitting the stored data value when accessed, wherein each the n single memory bit cell accessed in parallel to output a corresponding stored data value at a corresponding single read port in parallel at a respective local read bit line according to decoded address bits; and n selector devices, each selector device corresponding to a single memory bit cell and each simultaneously receiving a respective stored single bit cell data value transmitted on a respective local read bit line, in parallel, from each the accessed single memory bit cell, each selector device implementing selection logic based directly on the decoded address bits to select a respective local bit line output providing a stored single bit data value corresponding to the accessed single read port.

"Further to this aspect, the register file further comprises n decoder devices, a decoder device corresponding to a single bit cell and configured to receive predetermined bit signals of a read port memory address and an enable signal, a decoder device of the n decoder devices being selected by the enable signal to generate the decoded address bits corresponding to the predetermined bit signals.

"Furthermore, the register file further comprises: n clock control buffer devices, a clock control buffer device corresponding to a respective decoder device, each clock control buffer device for receiving the decoded address bit signals in parallel, and implementing logic to generate a respective output read word line signal, each the output read word line signal being input to a corresponding single bit memory cell for accessing the corresponding single bit cell.

"Further, the register file comprises: n clock control buffer devices, a clock control buffer device corresponding to a respective decoder device, each clock control buffer device for receiving said decoded address bit signals in parallel, and implementing logic to generate a respective output read word line signal, each said output read word line signal being input to a corresponding single bit memory cell for accessing said corresponding single bit cell.

"Further, a receiver device is coupled to receive from each local read bit lines the single bit cell data values transmitted in parallel from each accessed single memory bit cell read port, the receiver device simultaneously providing the data transmitted on each the respective local read bit line as inputs to each of the selector devices, each individual selector device selected based on the decoded address bits and the enable signal to generate a corresponding register file read port output bit.

"Further to this aspect, each selector device comprises a n:1 multiplexer logic device for simultaneously receiving the read port data values on the local read bit lines, and a selector means associated with each n:1 multiplexer logic device for selecting one of the local bit line data values as a corresponding register file read port output bit of a corresponding multiplexer logic device based on the generated decoded address bit signals and the enable signal.

"In one embodiment, a method of operating an n-port register file is provided where n is an integer equal to or greater than 2. The n-port register file includes n single memory bit cells each storing a single bit value and having a single bit cell write port, and a single read port connecting a respective local read bit line for outputting the stored data value when accessed. The method comprises: activating, in response to a register file read request, each n single memory bit cell in parallel to output a corresponding stored data value at a corresponding single read port for output in parallel at a respective local read bit line according to decoded address bits; simultaneously receiving, at each of n selector devices corresponding to the n single memory bit cells, the respective stored single bit cell data values transmitted on a respective local read bit line in parallel from each the accessed single memory bit cell; and implementing selection logic based directly on the decoded address bits at each of the n selector devices to select a respective local bit line output providing a stored single bit data value corresponding to the accessed single read port.

"Further to this embodiment, the method comprises: simultaneously receiving, at each of n decoder devices, predetermined bit signals of a read port memory address and an enable signal, one of the n decoder devices being selected by the enable signal to generate the decoded address bits corresponding to the predetermined bit signals.

"Further, the method comprises: receiving the decoded address bits in parallel at each respective clock control buffer device of n clock control buffers devices, and implementing logic at each clock control buffer device to generate a respective output read word line signal, each the output read word line signal being input to a corresponding single bit memory cell for accessing the corresponding single bit cell.

"The method further comprises: transmitting single bit cell data values in parallel from each the accessed single memory bit cell read port on respective the local read bit lines to each the n selector devices; and simultaneously receiving, at each the selector device, each the transmitted single bit cell data values from the local read bit lines, wherein the implementing logic at each the n selection logic device comprises: selecting, based on the decoded address bits and the enable signal, an individual selector device to generate a corresponding register file read port output bit; and generating, at each selected selector device, a corresponding register file read output bit according to received the decoder read address signals."

For the URL and additional information on this patent, see: Le, Thoai Thai; Atwal, Jagreet S.. Multiple Read Port Memory System with a Single Port Memory Cell. U.S. Patent Number 8811102, filed January 16, 2013, and published online on August 19, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8811102.PN.&OS=PN/8811102RS=PN/8811102

Keywords for this news article include: Electronics, Microprocessors, International Business Machines Corporation.

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Source: Electronics Newsweekly


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