News Column

Patent Issued for Memory Device and Systems Including the Same

September 3, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent by the inventors Kim, Gyu Hong (Seoul, KR); Jung, Jong Hoon (Hwaseong-si, KR), filed on August 22, 2012, was published online on August 19, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8811069 is assigned to Samsung Electronics Co., Ltd. (Suwon-si, KR).

The following quote was obtained by the news editors from the background information supplied by the inventors: "Apparatuses, devices, controllers, and systems consistent with the present inventive concept relate to a memory device, and more particularly, to a memory device for controlling an activation timing of a control signal for operating the memory device using a variable delay circuit and systems including the same.

"Semiconductor devices are divided into static random access memory (SRAM) that stores data using a latch and dynamic random access memory (DRAM) that stores data using a capacitor.

"As the size of an SRAM cell decreases with the development of process technology, the distribution of a basic process characteristic of a transistor included in the memory cell increases and the distribution of an SRAM characteristic such as a write margin, a static noise margin or a sense margin also increases.

"Due to these phenomena, an operation error occurs when an SRAM is operated using a delay set in the design stage. Since the delay cannot be changed in a related art SRAM, an SRAM having the operation error is rejected as faulty. As a result, the yield of the SRAM decreases."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "According to an aspect of one or more exemplary embodiments, there is provided a memory device including a memory cell array, an access control circuit configured to access the memory cell array to perform a read operation or a write operation, a control signal generation circuit configured to generate a control signal for controlling an operation of the access control circuit, and a variable delay circuit configured to generate a delay signal by variably delaying a clock signal according to an external signal. The control signal generation circuit may adjust an activation timing of the control signal in response to the delay signal.

"The variable delay circuit may include a delay setting circuit configured to set an amount of delay of the variable delay circuit according to the external signal, and a delay circuit configured to generate the delay signal by variably delaying the clock signal according to the amount of delay. The delay setting circuit may include a register configured to store the amount of delay.

"The delay circuit may include a plurality of delay elements connected in series to each other, and each of the delay elements may be a buffer or an inverter. Alternatively, the delay setting circuit may include a plurality of fusing elements, and the amount of delay may be determined according to a number of the fusing elements which are cut, or according to a number of fusing elements which are uncut. The memory device may be a static random access memory (SRAM).

"The control signal may be a sense amplifier enable signal for controlling an operation of a sense amplifier, a precharge enable signal for controlling the operation of the sense amplifier, a word line enable signal for controlling an operation of a row driver, or a column decoder enable signal for controlling an operation of a column decoder.

"According to another aspect of one or more exemplary embodiments, there is provided a memory controller including a memory device and a microprocessor configured to control an operation of the memory device. The memory device may include a memory cell array, an access control circuit configured to access the memory cell array to perform a read operation or a write operation, a control signal generation circuit configured to generate a control signal for controlling an operation of the access control circuit, and a variable delay circuit configured to generate a delay signal by variably delaying a clock signal according to an external signal. The control signal generation circuit may adjust an activation timing of the control signal in response to the delay signal.

"According to another aspect of one or more exemplary embodiments, there is provided a memory system including a nonvolatile memory and the above-described memory controller configured to control an operation of the nonvolatile memory device. The memory controller may write data output from the nonvolatile memory to the memory device using the access control circuit and transmit data from the access control circuit to the nonvolatile memory.

"According to another aspect of one or more exemplary embodiments, a memory system includes a display, a nonvolatile memory, and the above-described memory controller configured to transmit data from the nonvolatile memory to the display. The memory controller may write data output from the nonvolatile memory to the memory device using the access control circuit and transmit data from the access control circuit to the nonvolatile memory.

"According to another aspect of one or more exemplary embodiments, a memory card includes a card interface, a nonvolatile memory, and the above-described memory controller configured to interface with the card interface and the nonvolatile memory for data transmission.

"According to another aspect of one or more exemplary embodiments, a solid state drive includes at least one nonvolatile memory, the above-described memory controller configured to control a data processing operation of the at least one nonvolatile memory device, and a buffer manager configured to control data transmitted between the memory controller and a host to be stored in a volatile memory device."

URL and more information on this patent, see: Kim, Gyu Hong; Jung, Jong Hoon. Memory Device and Systems Including the Same. U.S. Patent Number 8811069, filed August 22, 2012, and published online on August 19, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8811069.PN.&OS=PN/8811069RS=PN/8811069

Keywords for this news article include: Random Access Memory, Samsung Electronics Co. Ltd.

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Source: Electronics Newsweekly


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