News Column

Patent Application Titled "User Registers Implemented with Routing Circuits in a Configurable Ic" Published Online

September 4, 2014



By a News Reporter-Staff News Editor at Politics & Government Week -- According to news reporting originating from Washington, D.C., by VerticalNews journalists, a patent application by the inventor Redgrave, Jason (Mountain View, CA), filed on February 14, 2014, was made available online on August 21, 2014.

The assignee for this patent application is Tabula Inc.

Reporters obtained the following quote from the background information supplied by the inventors: "The use of configurable integrated circuits ('IC's') has dramatically increased in recent years. One example of a configurable IC is a field programmable gate array ('FPGA'). An FPGA is a field programmable IC that often has logic circuits, interconnect circuits, and input/output (110) circuits. The logic circuits (also called logic blocks) are typically arranged as an internal array of circuits. These logic circuits are typically connected together through numerous interconnect circuits (also called interconnects). The logic and interconnect circuits are often surrounded by the I/O circuits. Like some other configurable IC's, the logic circuits and interconnect circuits of an FPGA are configurable.

"FIG. 1 illustrates an example of a configurable logic circuit 100. This logic circuit can be configured to perform a number of different functions. As shown in FIG. 1, the logic circuit 100 receives a set of input data 105 and a set of configuration data 110. The configuration data set is stored in a set of SRAM cells 115. From the set of functions that the logic circuit 100 can perform, the configuration data set specifies a particular function that this circuit has to perform on the input data set. Once the logic circuit performs its function on the input data set, it provides the output of this function on a set of output lines 120. The logic circuit 100 is said to be configurable, as the configuration data set 'configures' the logic circuit to perform a particular function, and this configuration data set can be modified by writing new data in the SRAM cells. Multiplexers and look-up tables are two examples of configurable logic circuits.

"FIG. 2 illustrates an example of a configurable interconnect circuit 200. This interconnect circuit 200 connects a set of input data 205 to a set of output data 210. This circuit receives configuration data bits 215 that are stored in a set of SRAM cells 220. The configuration bits specify how the interconnect circuit should connect the input data set to the output data set. The interconnect circuit 200 is said to be configurable, as the configuration data set 'configures' the interconnect circuit to use a particular connection scheme that connects the input data set to the output data set in a desired manner. Moreover, this configuration data set can be modified by writing new data in the SRAM cells. Multiplexers are one example of interconnect circuits.

"FIG. 3A conceptually illustrates a simplified portion of a prior art configurable IC 300 island style architecture. As shown in this figure, the IC 300 includes an array of configurable logic circuits 305 and configurable interconnect circuits 310. The IC 300 has two types of interconnect circuits 310a and 310b. Interconnect circuits 310a connect interconnect circuits 310b and logic circuits 305, while interconnect circuits 310b connect interconnect circuits 310a to other interconnect circuits 310a.

"In some cases, the IC 300 includes numerous logic circuits 305 and interconnect circuits 310 (e.g., hundreds, thousands, hundreds of thousands, etc. of such circuits). Each logic circuit 305 includes additional logic and interconnect circuits. Specifically, FIG. 3A illustrates a logic circuit 305a. As illustrated in FIG. 3B in more detail, this logic circuit includes two sections 315a that together are called a slice. Each section includes a look-up table (LUT) 320, a user register 325, a multiplexer 330, and possibly other circuitry (e.g., carry logic) not illustrated in FIG. 3B.

"As shown in FIG. 3B, the multiplexer 330 is responsible for selecting between the output of the LUT 320 or the user register 325. For instance, when the logic circuit 305a has to perform a computation through the LUT 320, the multiplexer 330 selects the output of the LUT 320. Alternatively, this multiplexer selects the output of the user register 325 when the logic circuit 305a or a slice of this circuit needs to store data for a future computation of the logic circuit 305a or another logic circuit.

"FIG. 3C illustrates an alternative way of constructing half a slice in a logic circuit 305a of FIG. 3A. Like the half-slice 315a in FIG. 3B, the half-slice 315b in FIG. 3C includes a look-up table (LUT) 320, a user register 325, a multiplexer 330, and possibly other circuitry (e.g., carry logic) not illustrated in FIG. 3C. However, in the half-slice 315b, the user register 325 can also be configured as a latch. In addition, the half-slice 315b also includes a multiplexer 350. In half-slice 315b, the multiplexer 350 receives the output of the LUT 320 instead of the register/latch 325, which receives this output in half-slice 315a. The multiplexer 350 also receives a signal from outside of the half-slice 315b. Based on its select signal, the multiplexer 350 then supplies one of the two signals that it receives to the register/latch 325. In this manner, the register/latch 325 can be used to store (1) the output signal of the LUT 320 or (2) a signal from outside the half-slice 315b.

"At times, the use of user registers to store such data is suboptimal, as it typically requires data to be passed at a clock's rising edge or a clock's falling edge. In other words, registers often do not provide flexible control over the data passing between the various circuits of the configurable IC. In addition, the placement of a register or a latch in the logic circuit increases the signal delay through the logic circuit, as it requires the use of at least one multiplexer 330 to select between the output of a register/latch 325 and the output of a LUT 320.

"Accordingly, there is a need for a configurable IC that has a more flexible approach for storing data and passing the data. More generally, there is a need for more flexible storage mechanisms in configurable IC's."

In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventor's summary information for this patent application: "Some embodiments of the invention provide a configurable integrated circuit ('IC'). The configurable IC includes a set of configurable logic circuits for configurably performing a set of functions. The configurable IC also includes a set of configurable routing circuits for routing signals to and from the configurable circuits. During several operational cycles of the configurable IC, a set of data registers are defined by the configurable routing circuits. These data registers may be used wherever a flip-flop can be used.

"Some embodiments provide a reconfigurable IC. This reconfigurable IC includes a set of reconfigurable circuits for reconfigurably performing a set of operations in more than one reconfiguration cycle. The reconfigurable IC also includes a set of reconfigurable circuits that perform a storage operation during one reconfiguration cycle and perform a non-storage operation during a second reconfiguration cycle. At least two of these reconfigurable circuits are communicatively coupled to operate as a data register during at least two reconfiguration cycles.

"Some embodiments provide a method of designing a configurable IC. The method includes receiving a first design that has at least one controllable circuit that is initialized by a first type of initialization signal. This first design also has at least one controllable circuit that is initialized by a second type of initialization signal. The method defines a second design based on the first design. The method defines this second design by replacing all controllable circuits that are initialized by the first type of initialization signal with functionally equivalent controllable circuits. Each of these functionally equivalent controllable circuits includes a particular controllable circuit that is initialized by the second type initialization signal.

BRIEF DESCRIPTION OF THE DRAWINGS

"The novel features of the invention are set forth in the appended claims. However, for purpose of explanation, several embodiments of the invention are set forth in the following figures.

"FIG. 1 illustrates an example of a prior art configurable logic circuit.

"FIG. 2 illustrates an example of a prior art configurable interconnect circuit.

"FIG. 3A illustrates a portion of a prior art configurable IC.

"FIG. 3B illustrates a prior art logic circuit.

"FIG. 3C illustrates an alternative way of constructing the logic circuit of FIG. 3B.

"FIG. 4 illustrates an example of a D-latch.

"FIG. 5 illustrates an example of a register, which is a D flip-flop.

"FIG. 6 illustrates the truth table of the flip-flop shown in FIG. 5.

"FIG. 7 illustrates a prior art implementation of a register with a pair of latches.

"FIG. 8 conceptually illustrates a configurable IC of some embodiments.

"FIG. 9 conceptually illustrates a user register implemented by connecting two interconnect/storage elements in a master/slave configuration.

"FIG. 10 illustrates a pair of master/slave interconnect/storage elements routing the output of the slave to a logic circuit.

"FIG. 11 illustrates a pair of master/slave interconnect/storage elements with a LUT receiving the output of the master.

"FIG. 12 illustrates a pair of master/slave interconnect/storage elements with a logic circuit and an RMUX between them.

"FIG. 13 conceptually illustrates an IC of some embodiments with several pairs RMUXs programmed to operate as master/slaves.

"FIG. 14 conceptually illustrates an edge-triggered user register.

"FIG. 15 illustrates an implementation of a user register using four RMUXs each operating on a different sub-cycle running four times faster than the user clock.

"FIG. 16 illustrates a user register operating on four sub-cycle implemented using only two RMUXs.

"FIG. 17 is an alternative to FIG. 16.

"FIG. 18 is another alternative to FIG. 16.

"FIG. 19 illustrates a user register implemented with three RMUXs.

"FIG. 20 is another alternative to FIG. 19.

"FIG. 21 illustrates a double-edge triggered user register of some embodiments.

"FIG. 22 illustrates a timing diagram of the user register of FIG. 21.

"FIG. 23 illustrates a reconfigurable IC of some embodiments implementing logical master/slave RMUX locations.

"FIG. 24 conceptually illustrates several user registers utilized for retiming signals between logic circuits in some embodiments.

"FIG. 25 illustrates logical structure of a Finite Impulse Response (FIR) filter FIR filter.

"FIG. 26 conceptually illustrates how some embodiments utilize user registers to implement a FIR filter.

"FIG. 27 conceptually illustrates a portion on a configurable IC of some embodiments.

"FIG. 28 conceptually illustrates a process that some embodiments use during synthesis to replace a design element with its equivalent.

"FIG. 29 illustrates a user register that has a set line.

"FIG. 30 illustrates a user register with a reset line and with its input and output lines inverted.

"FIG. 31 illustrates a user register with a reset line.

"FIG. 32 illustrates a user register with a set line and with its input and output lines inverted.

"FIG. 33 illustrates two ICs each with only one set or reset line.

"FIG. 34 conceptually illustrates an example of an electronics system that has an IC, which includes one of the invention's configurable circuit arrangements."

For more information, see this patent application: Redgrave, Jason. User Registers Implemented with Routing Circuits in a Configurable Ic. Filed February 14, 2014 and posted August 21, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4472&p=90&f=G&l=50&d=PG01&S1=20140814.PD.&OS=PD/20140814&RS=PD/20140814

Keywords for this news article include: Tabula Inc.

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