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Patent Application Titled "Process for Improving Package Warpage and Connection Reliability through Use of a Backside Mold Configuration (Bsmc)"...

September 4, 2014



Patent Application Titled "Process for Improving Package Warpage and Connection Reliability through Use of a Backside Mold Configuration (Bsmc)" Published Online

By a News Reporter-Staff News Editor at Politics & Government Week -- According to news reporting originating from Washington, D.C., by VerticalNews journalists, a patent application by the inventors Bchir, Omar James (San Marcos, CA); Shah, Milind Pravin (San Diego, CA); Movva, Sashidhar (San Diego, CA), filed on April 17, 2014, was made available online on August 21, 2014.

The assignee for this patent application is Qualcomm Incorporated.

Reporters obtained the following quote from the background information supplied by the inventors: "Packaged integrated circuits are continuously shrinking in thickness to fit smaller form factor electronic devices. As a result, the packaging substrate is shrinking in thickness, which reduces the stiffness of the packaging substrate. During manufacturing processes that apply heat to the substrate such as, for example, solder reflow, the substrate may warp. The warpage may be due to stress applied to the packaging substrate from differences in coefficients of thermal expansion between materials in the packaging substrate. When the packaging substrate warps, no-connects between the packaging substrate and the attached die may occur, resulting in electrical failure of the packaged integrated circuit.

"FIG. 1 is a cross-sectional view illustrating die non-connects resulting from substrate warpage in a conventional packaged integrated circuit. A packaged integrated circuit includes a packaging substrate 102 having a packaging connection 104. A die 112 is coupled to the packaging connection 104 through a packaging connection 114. When the packaging substrate 102 warps during manufacturing the packaging connection 104 may become disconnected from the packaging connection 114 in portions of the packaging integrated circuit.

"Additionally, during packaging of the integrated circuit, the packaging substrate has openings in a solder resist layer exposing contact pads of the packaging substrate. The openings are present in the packaging substrate before attaching the die to the packaging substrate. As a result, the contact pads of the packaging substrate are exposed to atmosphere during manufacturing processes such as heating, reflow, and deflux. High temperatures in these manufacturing process degrade the contact pad through oxidization, which reduces the reliability of electronic connections made to the contact pad.

"Thus, there is a need to more reliably package integrated circuits using thin substrates."

In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventors' summary information for this patent application: "According to one embodiment of the disclosure, an integrated circuit (IC) packaging method includes attaching a die to a first side of a substrate. The method also includes depositing a mold compound on a second side of the substrate before attaching the die to the first side of the substrate. The method further includes depositing a packaging connection on the second side of the substrate that couples to a contact pad on the second side of the substrate.

"According to another embodiment of the disclosure, an apparatus includes a substrate. The apparatus also includes a dielectric on a first side of the substrate. The apparatus further includes a mold compound on the dielectric. The apparatus also includes a packaging connection coupled to a contact pad on the first side of the substrate through the mold compound and the dielectric.

"According to yet another embodiment of the disclosure, an apparatus includes a substrate. The apparatus also includes a dielectric on a first side of the substrate. The apparatus further includes a packaging connection coupled to a contact pad on the first side of the substrate through the dielectric. The apparatus also includes means for improving packaging connection reliability on the first side of the substrate, in which the improving means surrounds the packaging connection.

"This has outlined, rather broadly, the features and technical advantages of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages of the disclosure will be described below. It should be appreciated by those skilled in the art that this disclosure may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the teachings of the disclosure as set forth in the appended claims. The novel features, which are believed to be characteristic of the disclosure, both as to its organization and method of operation, together with further objects and advantages, will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

"For a more complete understanding of the present disclosure, reference is now made to the following description taken in conjunction with the accompanying drawings.

"FIG. 1 is a cross-sectional view illustrating die non-connects resulting from substrate warpage in a conventional packaged integrated circuit.

"FIG. 2 is a flow chart illustrating an exemplary process for improving packaging connection reliability in packaged integrated circuits according to one embodiment.

"FIGS. 3A-3H are cross-sectional views illustrating an exemplary process for improving packaging connection reliability in packaged integrated circuits according to one embodiment.

"FIG. 4 is a flow chart illustrating an exemplary process for improving packaging connection reliability in packaged integrated circuits according to a second embodiment.

"FIGS. 5A-5E are cross-sectional views illustrating an exemplary process for improving packaging connection reliability in packaged integrated circuits according to the second embodiment.

"FIG. 6 is a block diagram showing an exemplary wireless communication system in which an embodiment of the disclosure may be advantageously employed.

"FIG. 7 is a block diagram illustrating a design workstation used for circuit, layout, and logic design of a semiconductor component according to one embodiment."

For more information, see this patent application: Bchir, Omar James; Shah, Milind Pravin; Movva, Sashidhar. Process for Improving Package Warpage and Connection Reliability through Use of a Backside Mold Configuration (Bsmc). Filed April 17, 2014 and posted August 21, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=2279&p=46&f=G&l=50&d=PG01&S1=20140814.PD.&OS=PD/20140814&RS=PD/20140814

Keywords for this news article include: Qualcomm Incorporated.

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Source: Politics & Government Week


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