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"Out-Of-Order Command Execution in Non-Volatile Memory" in Patent Application Approval Process

September 2, 2014



By a News Reporter-Staff News Editor at Information Technology Newsweekly -- A patent application by the inventors Gurgi, Eyal (Herzeliya, IL); Ish-Shalom, Tomer (Herzeliya, IL), filed on February 11, 2013, was made available online on August 21, 2014, according to news reporting originating from Washington, D.C., by VerticalNews correspondents.

This patent application is assigned to Apple Inc.

The following quote was obtained by the news editors from the background information supplied by the inventors: "In various data storage applications, a host issues a sequence of memory commands for execution in a memory. Various techniques are known in the art for processing sequences of memory commands. Some techniques improve performance by modifying the order in which the commands are executed.

"For example, U.S. Patent Application Publication 2009/0172263, whose disclosure is incorporated herein by reference, describes a storage controller connected to a Flash memory module. An execute loop in the storage controller is used to carry out tasks related to reading or writing data from the module. The loop includes reading a data structure from a queue and carrying out a task specified by the data structure, unless resources required by the task are not available, in which event the loop moves on to another data structure stored in another queue. Data structures bypassed by the loop are periodically revisited, until all tasks required are completed. Data structures store state information that is updated when tasks are completed."

In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventors' summary information for this patent application: "An embodiment of the present invention that is described herein provides a method including, in a memory controller that controls a memory, receiving at least one request causing execution of a sequence of memory commands in the memory. An identification is made that, although a first memory command appears in the sequence before a second memory command, the execution of the second memory command would improve a performance of the execution of the first memory command. The second memory command is executed, and then the first memory command is executed with the improved execution performance.

"In some embodiments, the first and second memory commands include read commands, and the performance includes a latency of the execution of the first memory command.

"In some embodiments, identifying that the execution of the second memory command would improve the performance of the first memory command includes identifying that the second memory command reads a lower page from a second group of memory cells and that the first memory command reads an upper page from a first group of memory cells. In an embodiment, the first group equals the second group. In a disclosed embodiment, executing the second memory command includes caching the read lower page, and executing the first memory command includes reading the upper page using the cached lower page.

"In another embodiment, executing the second memory command includes reading the memory cells in the second group using one or more second read thresholds, and executing the first memory command includes calculating one or more first read thresholds based on the second read thresholds, and reading the memory cells in the first group using the first read thresholds.

"In yet another embodiment, executing the second memory command includes caching the read lower page, and executing the first memory command includes calculating one or more first read thresholds based on the cached lower page, and reading the memory cells in the first group using the first read thresholds. In still another embodiment, executing the second memory command includes assessing a condition of the memory cells, and executing the first memory command includes reading the memory cells in the first group based on the assessed condition.

"In another embodiment, executing the second memory command and then the first memory command includes, for a given memory block of the memory, executing at least a predefined number of lower-page read commands in the sequence before executing any upper-page read command in the sequence. In an example embodiment, executing the second memory command includes estimating an interference in the second group, and executing the first memory command includes reading the memory cells in the first group based on the estimated interference.

"In some embodiments, identifying that the execution of the second memory command would improve the performance of the first memory command includes identifying that the second memory command reads one or more pages having a reduced level of interference. In an example embodiment, executing the second memory command includes learning a characteristic of the interference from the pages read by the second memory command, and executing the first memory command includes canceling the interference in at least one page read by the first memory command using the learned characteristic of the interference.

"In another embodiment, identifying that the second memory command reads one or more pages having a reduced interference level includes identifying that the second memory command reads one or more last pages in a memory block. In yet another embodiment, execution of the memory commands is performed by circuitry coupled to the memory, identification of the pages having the reduced level of interference is performed in a memory controller, and the method includes sending an instruction from the memory controller to the circuitry to retain the read pages having the reduced level of interference for future use in canceling the interference.

"In another embodiment, the first and second memory commands include respective first and second read commands, and identifying that the execution of the second memory command would improve the performance of the first memory command includes identifying that the second read command is expected to be decoded with fewer errors than the first read command.

"There is additionally provided, in accordance with an embodiment of the present invention, apparatus including an interface and storage circuitry. The interface is configured to communicate with a memory. The storage circuitry is configured to receive at least one request causing execution of a sequence of memory commands in the memory, to identify that, although a first memory command appears in the sequence before a second memory command, the execution of the second memory command would improve a performance of the execution of the first memory command, and to execute the second memory command and then to execute the first memory command with the improved execution performance.

"There is also provided, in accordance with an embodiment of the present invention, apparatus including a memory and storage circuitry. The storage circuitry is configured to receive at least one request causing execution of a sequence of memory commands in the memory, to identify that, although a first memory command appears in the sequence before a second memory command, the execution of the second memory command would improve a performance of the execution of the first memory command, and to execute the second memory command and then to execute the first memory command with the improved execution performance.

"The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which:

BRIEF DESCRIPTION OF THE DRAWINGS

"FIG. 1 is a block diagram that schematically illustrates a memory system, in accordance with an embodiment of the present invention; and

"FIGS. 2-4 are flow charts that schematically illustrate methods for executing sequences of memory commands, in accordance with embodiments of the present invention."

URL and more information on this patent application, see: Gurgi, Eyal; Ish-Shalom, Tomer. Out-Of-Order Command Execution in Non-Volatile Memory. Filed February 11, 2013 and posted August 21, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=415&p=9&f=G&l=50&d=PG01&S1=20140814.PD.&OS=PD/20140814&RS=PD/20140814

Keywords for this news article include: Apple Inc., Information Technology, Information and Data Architecture.

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Source: Information Technology Newsweekly


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