News Column

"Semiconductor Package and Method of Forming the Same" in Patent Application Approval Process

September 3, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent application by the inventor KIM, WOOJAE (Hwaseong-si, KR), filed on November 13, 2013, was made available online on August 21, 2014, according to news reporting originating from Washington, D.C., by VerticalNews correspondents.

This patent application is assigned to Samsung Electronics Co., Ltd.

The following quote was obtained by the news editors from the background information supplied by the inventors: "The disclosed subject matter relates to semiconductor packages and methods of forming the same.

"Semiconductor packages have been variously developed for their small size, lightness and low manufacture costs. Various kinds of the semiconductor packages have been used for various applications. A ball grid array (BGA) package may be formed by a mounting process, a molding process, and a solder ball bonding process. That is, a semiconductor chip may be mounted on a printed circuit board and then the molding process may be performed on the mounted semiconductor chip. Subsequently, the solder balls may be bonded to a bottom surface of the printed circuit board. The molding process should be required for the formation of the BGA package. Additionally, the BGA package uses the printed circuit board. Thus, size reduction of the BGA package may be limited. A wafer level package (WLP) package has been suggested in order to resolve the problems of the BGA package. In the WLP package, a redistribution pattern may be formed on a bottom surface of a semiconductor chip and then solder balls may be directly bonded to the redistribution pattern without a molding process. That is, the WLP package may not need the molding process and the printed circuit board. Thus, the WLP package may have a simple structure and a size of the WLP package may be reduced."

In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventor's summary information for this patent application: "Embodiments of the disclosed subject matter may provide semiconductor packages having improved reliability and a reduced size.

"Embodiments of the disclosed subject matter may also provide methods of forming a semiconductor package having improved reliability and a reduced size.

"In one aspect, a semiconductor package may include: a package substrate; a semiconductor chip mounted on the package substrate using a flip chip bonding technique; and a mold layer filling a space between the package substrate and the semiconductor chip. A sidewall of the semiconductor chip may not be covered by the mold layer but may be exposed.

"In some embodiments, the sidewall of the semiconductor chip may be substantially coplanar with sidewalls of the mold layer and the package substrate.

"In some embodiments, the semiconductor chip may include a chip part and a scribe lane part disposed at an edge of the chip part; and a sidewall of the scribe lane part may be exposed.

"In some embodiments, a step difference may occur between a bottom surface of the scribe lane part facing the package substrate and a bottom surface of the chip part facing the package substrate. In this case, a distance from the package substrate to the bottom surface of the scribe lane part may be greater than a distance from the package substrate to the bottom surface of the chip part. The sidewall of the scribe lane part may have a surface roughness different from that of a sidewall of the chip part.

"In some embodiments, a bottom surface of the scribe lane part may be substantially coplanar with a bottom surface of the chip part.

"In some embodiments, the semiconductor package may further include: an upper mold layer covering a top surface of the semiconductor chip and exposing the sidewall of the semiconductor chip.

"In another aspect, a method of forming a semiconductor package may include: cutting a wafer including chip parts and a scribe lane part between the chip parts to form individual semiconductor chips, each of the individual semiconductor chips including each of the chip parts and a scribe lane part disposed at an edge of each of the chip parts; mounting the individual semiconductor chips on a package substrate by using a flip chip bonding technique; filling spaces between the package substrate and the individual semiconductor chips with a mold layer; and successively cutting the mold layer and the package substrate.

"In some embodiments, cutting the wafer to form the individual semiconductor chips may include removing a portion of the scribe lane part of the wafer to form a groove exposing a sidewall of the chip part, the groove having a first width; and sawing the scribe lane part of a bottom of the groove by a blade having a second width less than the first width to form the individual semiconductor chips.

"In some embodiments, the groove may be formed using a laser.

"In some embodiments, the mold layer may be formed to extend onto top surfaces of the semiconductor chips.

BRIEF DESCRIPTION OF THE DRAWINGS

"The disclosed subject matter will become more apparent in view of the attached drawings and accompanying detailed description.

"FIG. 1 is a cross-sectional view illustrating a semiconductor package according to some embodiments of the disclosed subject matter;

"FIGS. 2 to 6 are cross-sectional views illustrating a method of forming a semiconductor device of FIG. 1;

"FIG. 7 is a cross-sectional view illustrating a semiconductor package according to other embodiments of the disclosed subject matter;

"FIG. 8 is a cross-sectional view illustrating a semiconductor package according to still other embodiments of the disclosed subject matter;

"FIG. 9 illustrates an example of package modules including semiconductor packages according to embodiments of the disclosed subject matter;

"FIG. 10 is a schematic block diagram illustrating an example of electronic systems including semiconductor packages according to embodiments of the disclosed subject matter; and

"FIG. 11 is a schematic block diagram illustrating an example of memory systems including semiconductor packages according to some embodiments of the disclosed subject matter.

"FIG. 12 is a flowchart illustrating an example of a technique according to embodiments of the disclosed subject matter."

URL and more information on this patent application, see: KIM, WOOJAE. Semiconductor Package and Method of Forming the Same. Filed November 13, 2013 and posted August 21, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4884&p=98&f=G&l=50&d=PG01&S1=20140814.PD.&OS=PD/20140814&RS=PD/20140814

Keywords for this news article include: Circuit Board, Semiconductor, Samsung Electronics Co. Ltd..

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


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Source: Electronics Newsweekly


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