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"Gate All around Semiconductor Device" in Patent Application Approval Process

September 3, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent application by the inventors Suk, Sung-Dae (Seoul, KR); Ha, Dae-Won (Seoul, KR); Park, Su-Yeon (Busanjin-gu, KR), filed on March 15, 2013, was made available online on August 21, 2014, according to news reporting originating from Washington, D.C., by VerticalNews correspondents.

This patent application is assigned to Samsung Electronics Co., Ltd.

The following quote was obtained by the news editors from the background information supplied by the inventors: "The present inventive concept relates to a gate all around (GAA) type semiconductor devices.

"As semiconductor devices are becoming highly integrated, a size of an active region has been reduced, and thus a channel length of a transistor formed in the active region has been reduced. As the channel length of the MOS transistor is reduced, a short channel effect, e.g., an effect of a source/drain region on an electric field of a channel region, may be increased and a channel driving capability of a gate electrode may be deteriorated. In a GAA type semiconductor device, a channel is surrounded by a gate electrode, and an effect of a source/drain region on an electric field of a channel region may be reduced to suppress a short channel effect."

In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventors' summary information for this patent application: "The present inventive concept provides a gate all around (GAA) type semiconductor device, which can reduce resistance of a source/drain region.

"The present inventive concept also provides a GAA type semiconductor device, which can increase boosting of a source/drain region.

"These and other objects of the present inventive concept will be described in or be apparent from the following description of the preferred embodiments.

"According to an aspect of the present inventive concept, there is provided a gate all around (GAA) type semiconductor device including source/drain layers formed to be spaced apart from each other, a channel layer connecting the source/drain layers, and a gate electrode formed along the periphery of at least a portion of the channel layer, wherein lower portions of the source/drain layers are formed more deeply than the channel layer, and an insulation pattern is formed between the lower portions of the source/drain layers and lower portions of the gate electrode.

"According to another aspect of the present inventive concept, there is provided a gate all around (GAA) type semiconductor device including source/drain layers formed to be spaced apart from each other, a channel layer connecting the source/drain layers, a gate electrode formed along the periphery of at least a portion of the channel layer, a gate insulation layer surrounding the periphery of at least a portion of the channel layer and positioned between the channel layer and the gate electrode, and a spacer formed on the gate electrode and between upper portions of the source/drain layers, wherein a lower portion of the gate electrode is formed to the same depth as the lower portions of the source/drain layers.

"Some embodiments are directed to semiconductor devices that include source/drain layers that are formed at a first depth in a substrate and spaced apart from each other, a channel layer that is formed at a second depth in the substrate that is less deep than the first depth and connecting the source/drain layers, a gate electrode that is formed along a periphery of at least a portion of the channel layer, and an insulation pattern that is formed between lower portions of the source/drain layers and corresponding lower portions of the gate electrode.

"It is noted that aspects of the inventive concept described with respect to one embodiment, may be incorporated in a different embodiment although not specifically described relative thereto. That is, all embodiments and/or features of any embodiment can be combined in any way and/or combination. These and other objects and/or aspects of the present inventive concept are explained in detail in the specification set forth below.

BRIEF DESCRIPTION OF THE DRAWINGS

"The accompanying figures are included to provide a further understanding of the present inventive concept, and are incorporated in and constitute a part of this specification. The drawings illustrate some embodiments of the present inventive concept and, together with the description, serve to explain principles of the present inventive concept.

"FIG. 1 is a perspective view illustrating a GAA type semiconductor device according to some embodiments of the present inventive concept.

"FIG. 2 is a cross-sectional view illustrating the GAA type semiconductor device according to embodiments of the present inventive concept, taken along the line A-A' of FIG. 1.

"FIG. 3 is a cross-sectional view illustrating the GAA type semiconductor device according to embodiments of the present inventive concept, taken along the line B-B' of FIG. 1.

"FIG. 4 is a cross-sectional view illustrating an application example of the GAA type semiconductor device according to embodiments of the present inventive concept, taken along the same line as the line A-A' of FIG. 1.

"FIG. 5 is a cross-sectional view illustrating an application example of the GAA type semiconductor device according to embodiments of the present inventive concept, taken along the same line as the line B-B' of FIG. 1.

"FIG. 6 is a cross-sectional view illustrating a GAA type semiconductor device according to some embodiments of the present inventive concept, taken along the same line as the line A-A' of FIG. 1.

"FIG. 7 is a cross-sectional view illustrating the GAA type semiconductor device according to embodiments of the present inventive concept, taken along the same line as the line B-B' of FIG. 1.

"FIGS. 8 to 17 are perspective views illustrating intermediate process operations for explaining example fabricating methods of the GAA type semiconductor device according to some embodiments of the present inventive concept.

"FIG. 18 is a perspective view illustrating intermediate process operation for explaining example fabricating methods of an application example of the GAA type semiconductor device according to some embodiments of the present inventive concept.

"FIGS. 19 and 20 are perspective views illustrating intermediate process operations for explaining example fabricating methods of the GAA type semiconductor device according to some embodiments of the present inventive concept.

"FIG. 21 is a block diagram of an electronic system including semiconductor devices according to some embodiments of the present inventive concept."

URL and more information on this patent application, see: Suk, Sung-Dae; Ha, Dae-Won; Park, Su-Yeon. Gate All around Semiconductor Device. Filed March 15, 2013 and posted August 21, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4945&p=99&f=G&l=50&d=PG01&S1=20140814.PD.&OS=PD/20140814&RS=PD/20140814

Keywords for this news article include: Semiconductor, Samsung Electronics Co. Ltd..

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Source: Electronics Newsweekly


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